1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2007,2008 Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 * Copyright (C) 2008 Renesas Solutions Corp.
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
14 #include <asm/processor.h>
16 #define CMT_CMCSR_INIT 0x0001 /* PCLK/32 */
17 #define CMT_CMCSR_CALIB 0x0000
18 #define CMT_MAX_COUNTER (0xFFFFFFFF)
19 #define CMT_TIMER_RESET (0xFFFF)
21 static vu_long cmt0_timer;
23 static void cmt_timer_start(unsigned int timer)
25 writew(readw(CMSTR) | 0x01, CMSTR);
28 static void cmt_timer_stop(unsigned int timer)
30 writew(readw(CMSTR) & ~0x01, CMSTR);
36 /* Divide clock by 32 */
38 writew(CMT_CMCSR_INIT, CMCSR_0);
40 /* User Device 0 only */
42 writew(CMT_TIMER_RESET, CMCOR_0);
48 unsigned long long get_ticks(void)
53 static vu_long cmcnt = 0;
54 static unsigned long get_usec (void)
56 ulong data = readw(CMCNT_0);
61 cmcnt = (CMT_TIMER_RESET - cmcnt) + data;
63 if ((cmt0_timer + cmcnt) > CMT_MAX_COUNTER)
64 cmt0_timer = ((cmt0_timer + cmcnt) - CMT_MAX_COUNTER);
73 ulong get_timer(ulong base)
75 return (get_usec() / 1000) - base;
78 void __udelay(unsigned long usec)
80 unsigned long end = get_usec() + usec;
82 while (get_usec() < end)
86 unsigned long get_tbclk(void)
88 return CONFIG_SH_CMT_CLK_FREQ;