arch/powerpc/dts/t102x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * T102X Silicon/SoC Device Tree Source (pre include)
   4  *
   5  * Copyright 2013 Freescale Semiconductor Inc.
   6  * Copyright 2019-2020 NXP
   7  */
   8
   9 /dts-v1/;
  10
  11 /include/ "e5500_power_isa.dtsi"
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: PowerPC,e5500@0 {
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         #cooling-cells = <2>;
  26                 };
  27                 cpu1: PowerPC,e5500@1 {
  28                         device_type = "cpu";
  29                         reg = <1>;
  30                         #cooling-cells = <2>;
  31                 };
  32         };
  33
  34         soc: soc@ffe000000 {
  35                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  36                 reg = <0xf 0xfe000000 0 0x00001000>;
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 device_type = "soc";
  40                 compatible = "simple-bus";
  41
  42                 mpic: pic@40000 {
  43                         interrupt-controller;
  44                         #address-cells = <0>;
  45                         #interrupt-cells = <4>;
  46                         reg = <0x40000 0x40000>;
  47                         compatible = "fsl,mpic", "chrp,open-pic";
  48                         device_type = "open-pic";
  49                         clock-frequency = <0x0>;
  50                 };
  51
  52                 usb0@210000 {
  53                         compatible = "fsl-usb2-mph";
  54                         reg = <0x210000 0x1000>;
  55                         phy_type = "utmi";
  56                 };
  57
  58                 usb1@211000 {
  59                         compatible = "fsl-usb2-dr";
  60                         reg = <0x211000 0x1000>;
  61                         phy_type = "utmi";
  62                 };
  63
  64                 sata: sata@220000 {
  65                         compatible = "fsl,pq-sata-v2";
  66                         reg = <0x220000 0x1000>;
  67                         interrupts = <68 0x2 0 0>;
  68                         sata-offset = <0x1000>;
  69                         sata-number = <2>;
  70                         sata-fpdma = <0>;
  71                 };
  72
  73                 esdhc: esdhc@114000 {
  74                         compatible = "fsl,esdhc";
  75                         reg = <0x114000 0x1000>;
  76                         clock-frequency = <0>;
  77                 };
  78                 /include/ "qoriq-i2c-0.dtsi"
  79                 /include/ "qoriq-i2c-1.dtsi"
  80         };
  81
  82         pcie@ffe240000 {
  83                 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
  84                 reg = <0xf 0xfe240000 0x0 0x1000>;   /* registers */
  85                 law_trgt_if = <0>;
  86                 #address-cells = <3>;
  87                 #size-cells = <2>;
  88                 device_type = "pci";
  89                 bus-range = <0x0 0xff>;
  90                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
  91                           0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
  92         };
  93
  94         pcie@ffe250000 {
  95                 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
  96                 reg = <0xf 0xfe250000 0x0 0x1000>;   /* registers */
  97                 law_trgt_if = <1>;
  98                 #address-cells = <3>;
  99                 #size-cells = <2>;
 100                 device_type = "pci";
 101                 bus-range = <0x0 0xff>;
 102                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
 103                           0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
 104         };
 105
 106         pcie@ffe260000 {
 107                 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
 108                 reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
 109                 law_trgt_if = <2>;
 110                 #address-cells = <3>;
 111                 #size-cells = <2>;
 112                 device_type = "pci";
 113                 bus-range = <0x0 0xff>;
 114                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
 115                           0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
 116         };
 117 };