arch/powerpc/dts/p2020-post.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P2020 Silicon/SoC Device Tree Source (post include)
   4  *
   5  * Copyright 2013 Freescale Semiconductor Inc.
   6  * Copyright 2019 NXP
   7  */
   8
   9 &soc {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         device_type = "soc";
  13         compatible = "fsl,p2020-immr", "simple-bus";
  14         bus-frequency = <0x0>;
  15
  16         usb@22000 {
  17                 compatible = "fsl-usb2-dr";
  18                 reg = <0x22000 0x1000>;
  19                 phy_type = "ulpi";
  20         };
  21
  22         mpic: pic@40000 {
  23                 interrupt-controller;
  24                 #address-cells = <0>;
  25                 #interrupt-cells = <4>;
  26                 reg = <0x40000 0x40000>;
  27                 compatible = "fsl,mpic";
  28                 device_type = "open-pic";
  29                 big-endian;
  30                 single-cpu-affinity;
  31                 last-interrupt-source = <255>;
  32         };
  33
  34         esdhc: esdhc@2e000 {
  35                 compatible = "fsl,esdhc";
  36                 reg = <0x2e000 0x1000>;
  37                 /* Filled in by U-Boot */
  38                 clock-frequency = <0>;
  39         };
  40
  41         /include/ "pq3-i2c-0.dtsi"
  42         /include/ "pq3-i2c-1.dtsi"
  43 };
  44
  45 /* PCIe controller base address 0x8000 */
  46 &pci2 {
  47         compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  48         law_trgt_if = <0>;
  49         #address-cells = <3>;
  50         #size-cells = <2>;
  51         device_type = "pci";
  52         bus-range = <0x0 0xff>;
  53 };
  54
  55 /* PCIe controller base address 0x9000 */
  56 &pci1 {
  57         compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  58         law_trgt_if = <1>;
  59         #address-cells = <3>;
  60         #size-cells = <2>;
  61         device_type = "pci";
  62         bus-range = <0x0 0xff>;
  63 };
  64
  65 /* PCIe controller base address 0xa000 */
  66 &pci0 {
  67         compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  68         law_trgt_if = <2>;
  69         #address-cells = <3>;
  70         #size-cells = <2>;
  71         device_type = "pci";
  72         bus-range = <0x0 0xff>;
  73 };