1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
5 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
15 #include <asm/cache.h>
18 #include <asm/fsl_law.h>
21 DECLARE_GLOBAL_DATA_PTR;
24 * Default board reset function
31 void board_reset(void) __attribute__((weak, alias("__board_reset")));
40 char buf1[32], buf2[32];
41 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
42 volatile ccsr_gur_t *gur = &immap->im_gur;
44 uint msscr0 = mfspr(MSSCR0);
50 if (cpu_numcores() > 1) {
52 puts("Unicore software on multiprocessor system!!\n"
53 "To enable mutlticore build define CONFIG_MP\n");
62 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
66 major = PVR_E600_MAJ(pvr);
67 minor = PVR_E600_MIN(pvr);
69 printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
70 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
71 puts("\n Core1Translation Enabled");
72 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
74 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
76 get_sys_info(&sysinfo);
78 puts("Clock Configuration:\n");
79 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
80 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
81 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
82 strmhz(buf1, sysinfo.freq_systembus / 2),
83 strmhz(buf2, sysinfo.freq_systembus));
85 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
86 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
88 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
89 sysinfo.freq_localbus);
92 puts("L1: D-cache 32 KiB enabled\n");
93 puts(" I-cache 32 KiB enabled\n");
96 if (get_l2cr() & 0x80000000) {
97 #if defined(CONFIG_ARCH_MPC8610)
99 #elif defined(CONFIG_ARCH_MPC8641)
102 puts(" KiB enabled\n");
111 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
113 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
114 volatile ccsr_gur_t *gur = &immap->im_gur;
116 /* Attempt board-specific reset */
119 /* Next try asserting HRESET_REQ */
120 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
130 * Get timebase clock frequency
137 get_sys_info(&sys_info);
138 return (sys_info.freq_systembus + 3L) / 4L;
142 #if defined(CONFIG_WATCHDOG)
146 #if defined(CONFIG_ARCH_MPC8610)
148 * This actually feed the hard enabled watchdog.
150 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
151 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
152 volatile ccsr_gur_t *gur = &immap->im_gur;
153 u32 tmp = gur->pordevsr;
161 #endif /* CONFIG_WATCHDOG */
164 * Print out the state of various machine registers.
165 * Currently prints out LAWs, BR0/OR0, and BATs
167 void print_reginfo(void)
175 * Set the DDR BATs to reflect the actual size of DDR.
177 * dram_size is the actual size of DDR, in bytes
179 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
180 * are using a single BAT to cover DDR.
182 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
183 * is not defined) then we might have a situation where U-Boot will attempt
184 * to relocated itself outside of the region mapped by DBAT0.
185 * This will cause a machine check.
187 * Currently we are limited to power of two sized DDR since we only use a
188 * single bat. If a non-power of two size is used that is less than
189 * CONFIG_MAX_MEM_MAPPED u-boot will crash.
192 void setup_ddr_bat(phys_addr_t dram_size)
194 unsigned long batu, bl;
196 bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
198 if (BATU_SIZE(bl) != dram_size) {
199 u64 sz = (u64)dram_size - BATU_SIZE(bl);
200 print_size(sz, " left unmapped\n");
203 batu = bl | BATU_VS | BATU_VP;
204 write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
205 write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);