arch/powerpc/cpu/mpc85xx/fdt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  */
   8
   9 #include <common.h>
  10 #include <clock_legacy.h>
  11 #include <env.h>
  12 #include <log.h>
  13 #include <time.h>
  14 #include <linux/libfdt.h>
  15 #include <fdt_support.h>
  16 #include <asm/processor.h>
  17 #include <linux/ctype.h>
  18 #include <asm/io.h>
  19 #include <asm/fsl_fdt.h>
  20 #include <asm/fsl_portals.h>
  21 #include <fsl_qbman.h>
  22 #include <hwconfig.h>
  23 #ifdef CONFIG_FSL_ESDHC
  24 #include <fsl_esdhc.h>
  25 #endif
  26 #ifdef CONFIG_SYS_DPAA_FMAN
  27 #include <fsl_fman.h>
  28 #endif
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 extern void ft_qe_setup(void *blob);
  33 extern void ft_fixup_num_cores(void *blob);
  34 extern void ft_srio_setup(void *blob);
  35
  36 #ifdef CONFIG_MP
  37 #include "mp.h"
  38
  39 void ft_fixup_cpu(void *blob, u64 memory_limit)
  40 {
  41         int off;
  42         phys_addr_t spin_tbl_addr = get_spin_phys_addr();
  43         u32 bootpg = determine_mp_bootpg(NULL);
  44         u32 id = get_my_id();
  45         const char *enable_method;
  46 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  47         int ret;
  48         int tdm_hwconfig_enabled = 0;
  49         char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  50 #endif
  51
  52         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  53         while (off != -FDT_ERR_NOTFOUND) {
  54                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  55
  56                 if (reg) {
  57                         u32 phys_cpu_id = thread_to_core(*reg);
  58                         u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
  59                         val = cpu_to_fdt64(val);
  60                         if (*reg == id) {
  61                                 fdt_setprop_string(blob, off, "status",
  62                                                                 "okay");
  63                         } else {
  64                                 fdt_setprop_string(blob, off, "status",
  65                                                                 "disabled");
  66                         }
  67
  68                         if (hold_cores_in_reset(0)) {
  69 #ifdef CONFIG_FSL_CORENET
  70                                 /* Cores held in reset, use BRR to release */
  71                                 enable_method = "fsl,brr-holdoff";
  72 #else
  73                                 /* Cores held in reset, use EEBPCR to release */
  74                                 enable_method = "fsl,eebpcr-holdoff";
  75 #endif
  76                         } else {
  77                                 /* Cores out of reset and in a spin-loop */
  78                                 enable_method = "spin-table";
  79
  80                                 fdt_setprop(blob, off, "cpu-release-addr",
  81                                                 &val, sizeof(val));
  82                         }
  83
  84                         fdt_setprop_string(blob, off, "enable-method",
  85                                                         enable_method);
  86                 } else {
  87                         printf ("cpu NULL\n");
  88                 }
  89                 off = fdt_node_offset_by_prop_value(blob, off,
  90                                 "device_type", "cpu", 4);
  91         }
  92
  93 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  94 #define CONFIG_MEM_HOLE_16M     0x1000000
  95         /*
  96          * Extract hwconfig from environment.
  97          * Search for tdm entry in hwconfig.
  98          */
  99         ret = env_get_f("hwconfig", buffer, sizeof(buffer));
 100         if (ret > 0)
 101                 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
 102
 103         /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
 104         if (tdm_hwconfig_enabled) {
 105                 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
 106                                       CONFIG_MEM_HOLE_16M);
 107                 if (off < 0)
 108                         printf("Failed  to reserve memory for tdm: %s\n",
 109                                fdt_strerror(off));
 110         }
 111 #endif
 112
 113         /* Reserve the boot page so OSes dont use it */
 114         if ((u64)bootpg < memory_limit) {
 115                 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
 116                 if (off < 0)
 117                         printf("Failed to reserve memory for bootpg: %s\n",
 118                                 fdt_strerror(off));
 119         }
 120
 121 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
 122         /*
 123          * Reserve the default boot page so OSes dont use it.
 124          * The default boot page is always mapped to bootpg above using
 125          * boot page translation.
 126          */
 127         if (0xfffff000ull < memory_limit) {
 128                 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
 129                 if (off < 0) {
 130                         printf("Failed to reserve memory for 0xfffff000: %s\n",
 131                                 fdt_strerror(off));
 132                 }
 133         }
 134 #endif
 135
 136         /* Reserve spin table page */
 137         if (spin_tbl_addr < memory_limit) {
 138                 off = fdt_add_mem_rsv(blob,
 139                         (spin_tbl_addr & ~0xffful), 4096);
 140                 if (off < 0)
 141                         printf("Failed to reserve memory for spin table: %s\n",
 142                                 fdt_strerror(off));
 143         }
 144 #ifdef CONFIG_DEEP_SLEEP
 145 #ifdef CONFIG_SPL_MMC_BOOT
 146         off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
 147                 CONFIG_SYS_MMC_U_BOOT_SIZE);
 148         if (off < 0)
 149                 printf("Failed to reserve memory for SD deep sleep: %s\n",
 150                        fdt_strerror(off));
 151 #elif defined(CONFIG_SPL_SPI_BOOT)
 152         off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
 153                 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
 154         if (off < 0)
 155                 printf("Failed to reserve memory for SPI deep sleep: %s\n",
 156                        fdt_strerror(off));
 157 #endif
 158 #endif
 159 }
 160 #endif
 161
 162 #ifdef CONFIG_SYS_FSL_CPC
 163 static inline void ft_fixup_l3cache(void *blob, int off)
 164 {
 165         u32 line_size, num_ways, size, num_sets;
 166         cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
 167         u32 cfg0 = in_be32(&cpc->cpccfg0);
 168
 169         size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
 170         num_ways = CPC_CFG0_NUM_WAYS(cfg0);
 171         line_size = CPC_CFG0_LINE_SZ(cfg0);
 172         num_sets = size / (line_size * num_ways);
 173
 174         fdt_setprop(blob, off, "cache-unified", NULL, 0);
 175         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 176         fdt_setprop_cell(blob, off, "cache-size", size);
 177         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 178         fdt_setprop_cell(blob, off, "cache-level", 3);
 179 #ifdef CONFIG_SYS_CACHE_STASHING
 180         fdt_setprop_cell(blob, off, "cache-stash-id", 1);
 181 #endif
 182 }
 183 #else
 184 #define ft_fixup_l3cache(x, y)
 185 #endif
 186
 187 #if defined(CONFIG_L2_CACHE) || \
 188         defined(CONFIG_BACKSIDE_L2_CACHE) || \
 189         defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 190 static inline void ft_fixup_l2cache_compatible(void *blob, int off)
 191 {
 192         int len;
 193         struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 194
 195         if (cpu) {
 196                 char buf[40];
 197
 198                 if (isdigit(cpu->name[0])) {
 199                         /* MPCxxxx, where xxxx == 4-digit number */
 200                         len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
 201                                 cpu->name) + 1;
 202                 } else {
 203                         /* Pxxxx or Txxxx, where xxxx == 4-digit number */
 204                         len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
 205                         tolower(cpu->name[0]), cpu->name + 1) + 1;
 206                 }
 207
 208                 /*
 209                  * append "cache" after the NULL character that the previous
 210                  * sprintf wrote.  This is how a device tree stores multiple
 211                  * strings in a property.
 212                  */
 213                 len += sprintf(buf + len, "cache") + 1;
 214
 215                 fdt_setprop(blob, off, "compatible", buf, len);
 216         }
 217 }
 218 #endif
 219
 220 #if defined(CONFIG_L2_CACHE)
 221 /* return size in kilobytes */
 222 static inline u32 l2cache_size(void)
 223 {
 224         volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 225         volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
 226         u32 ver = SVR_SOC_VER(get_svr());
 227
 228         switch (l2siz_field) {
 229         case 0x0:
 230                 break;
 231         case 0x1:
 232                 if (ver == SVR_8540 || ver == SVR_8560   ||
 233                     ver == SVR_8541 || ver == SVR_8555)
 234                         return 128;
 235                 else
 236                         return 256;
 237                 break;
 238         case 0x2:
 239                 if (ver == SVR_8540 || ver == SVR_8560   ||
 240                     ver == SVR_8541 || ver == SVR_8555)
 241                         return 256;
 242                 else
 243                         return 512;
 244                 break;
 245         case 0x3:
 246                 return 1024;
 247                 break;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static inline void ft_fixup_l2cache(void *blob)
 254 {
 255         int off;
 256         u32 *ph;
 257
 258         const u32 line_size = 32;
 259         const u32 num_ways = 8;
 260         const u32 size = l2cache_size() * 1024;
 261         const u32 num_sets = size / (line_size * num_ways);
 262
 263         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 264         if (off < 0) {
 265                 debug("no cpu node fount\n");
 266                 return;
 267         }
 268
 269         ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 270
 271         if (ph == NULL) {
 272                 debug("no next-level-cache property\n");
 273                 return ;
 274         }
 275
 276         off = fdt_node_offset_by_phandle(blob, *ph);
 277         if (off < 0) {
 278                 printf("%s: %s\n", __func__, fdt_strerror(off));
 279                 return ;
 280         }
 281
 282         ft_fixup_l2cache_compatible(blob, off);
 283         fdt_setprop(blob, off, "cache-unified", NULL, 0);
 284         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 285         fdt_setprop_cell(blob, off, "cache-size", size);
 286         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 287         fdt_setprop_cell(blob, off, "cache-level", 2);
 288
 289         /* we dont bother w/L3 since no platform of this type has one */
 290 }
 291 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
 292         defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 293 static inline void ft_fixup_l2cache(void *blob)
 294 {
 295         int off, l2_off, l3_off = -1;
 296         u32 *ph;
 297 #ifdef  CONFIG_BACKSIDE_L2_CACHE
 298         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 299 #else
 300         struct ccsr_cluster_l2 *l2cache =
 301                 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
 302         u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
 303 #endif
 304         u32 size, line_size, num_ways, num_sets;
 305         int has_l2 = 1;
 306
 307         /* P2040/P2040E has no L2, so dont set any L2 props */
 308         if (SVR_SOC_VER(get_svr()) == SVR_P2040)
 309                 has_l2 = 0;
 310
 311         size = (l2cfg0 & 0x3fff) * 64 * 1024;
 312         num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
 313         line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
 314         num_sets = size / (line_size * num_ways);
 315
 316         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 317
 318         while (off != -FDT_ERR_NOTFOUND) {
 319                 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 320
 321                 if (ph == NULL) {
 322                         debug("no next-level-cache property\n");
 323                         goto next;
 324                 }
 325
 326                 l2_off = fdt_node_offset_by_phandle(blob, *ph);
 327                 if (l2_off < 0) {
 328                         printf("%s: %s\n", __func__, fdt_strerror(off));
 329                         goto next;
 330                 }
 331
 332                 if (has_l2) {
 333 #ifdef CONFIG_SYS_CACHE_STASHING
 334                         u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 335 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 336                         /* Only initialize every eighth thread */
 337                         if (reg && !((*reg) % 8)) {
 338                                 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 339                                                  (*reg / 4) + 32 + 1);
 340                         }
 341 #else
 342                         if (reg) {
 343                                 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 344                                                  (*reg * 2) + 32 + 1);
 345                         }
 346 #endif
 347 #endif
 348
 349                         fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
 350                         fdt_setprop_cell(blob, l2_off, "cache-block-size",
 351                                                 line_size);
 352                         fdt_setprop_cell(blob, l2_off, "cache-size", size);
 353                         fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
 354                         fdt_setprop_cell(blob, l2_off, "cache-level", 2);
 355                         ft_fixup_l2cache_compatible(blob, l2_off);
 356                 }
 357
 358                 if (l3_off < 0) {
 359                         ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
 360
 361                         if (ph == NULL) {
 362                                 debug("no next-level-cache property\n");
 363                                 goto next;
 364                         }
 365                         l3_off = *ph;
 366                 }
 367 next:
 368                 off = fdt_node_offset_by_prop_value(blob, off,
 369                                 "device_type", "cpu", 4);
 370         }
 371         if (l3_off > 0) {
 372                 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
 373                 if (l3_off < 0) {
 374                         printf("%s: %s\n", __func__, fdt_strerror(off));
 375                         return ;
 376                 }
 377                 ft_fixup_l3cache(blob, l3_off);
 378         }
 379 }
 380 #else
 381 #define ft_fixup_l2cache(x)
 382 #endif
 383
 384 static inline void ft_fixup_cache(void *blob)
 385 {
 386         int off;
 387
 388         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 389
 390         while (off != -FDT_ERR_NOTFOUND) {
 391                 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
 392                 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
 393                 u32 isize, iline_size, inum_sets, inum_ways;
 394                 u32 dsize, dline_size, dnum_sets, dnum_ways;
 395
 396                 /* d-side config */
 397                 dsize = (l1cfg0 & 0x7ff) * 1024;
 398                 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
 399                 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
 400                 dnum_sets = dsize / (dline_size * dnum_ways);
 401
 402                 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
 403                 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 404                 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 405
 406 #ifdef CONFIG_SYS_CACHE_STASHING
 407                 {
 408                         u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 409                         if (reg)
 410                                 fdt_setprop_cell(blob, off, "cache-stash-id",
 411                                          (*reg * 2) + 32 + 0);
 412                 }
 413 #endif
 414
 415                 /* i-side config */
 416                 isize = (l1cfg1 & 0x7ff) * 1024;
 417                 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
 418                 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
 419                 inum_sets = isize / (iline_size * inum_ways);
 420
 421                 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
 422                 fdt_setprop_cell(blob, off, "i-cache-size", isize);
 423                 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
 424
 425                 off = fdt_node_offset_by_prop_value(blob, off,
 426                                 "device_type", "cpu", 4);
 427         }
 428
 429         ft_fixup_l2cache(blob);
 430 }
 431
 432
 433 void fdt_add_enet_stashing(void *fdt)
 434 {
 435         do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
 436
 437         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
 438
 439         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
 440         do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
 441         do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
 442         do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
 443 }
 444
 445 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
 446 #ifdef CONFIG_SYS_DPAA_FMAN
 447 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
 448                           unsigned long freq)
 449 {
 450         phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
 451         int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
 452
 453         if (off >= 0) {
 454                 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
 455                 if (off > 0)
 456                         printf("WARNING enable to set clock-frequency "
 457                                 "for %s: %s\n", compat, fdt_strerror(off));
 458         }
 459 }
 460 #endif
 461
 462 static void ft_fixup_dpaa_clks(void *blob)
 463 {
 464         sys_info_t sysinfo;
 465
 466         get_sys_info(&sysinfo);
 467 #ifdef CONFIG_SYS_DPAA_FMAN
 468         ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
 469                         sysinfo.freq_fman[0]);
 470
 471 #if (CONFIG_SYS_NUM_FMAN == 2)
 472         ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
 473                         sysinfo.freq_fman[1]);
 474 #endif
 475 #endif
 476
 477 #ifdef CONFIG_SYS_DPAA_QBMAN
 478         do_fixup_by_compat_u32(blob, "fsl,qman",
 479                         "clock-frequency", sysinfo.freq_qman, 1);
 480 #endif
 481
 482 #ifdef CONFIG_SYS_DPAA_PME
 483         do_fixup_by_compat_u32(blob, "fsl,pme",
 484                 "clock-frequency", sysinfo.freq_pme, 1);
 485 #endif
 486 }
 487 #else
 488 #define ft_fixup_dpaa_clks(x)
 489 #endif
 490
 491 #ifdef CONFIG_QE
 492 static void ft_fixup_qe_snum(void *blob)
 493 {
 494         unsigned int svr;
 495
 496         svr = mfspr(SPRN_SVR);
 497         if (SVR_SOC_VER(svr) == SVR_8569) {
 498                 if(IS_SVR_REV(svr, 1, 0))
 499                         do_fixup_by_compat_u32(blob, "fsl,qe",
 500                                 "fsl,qe-num-snums", 46, 1);
 501                 else
 502                         do_fixup_by_compat_u32(blob, "fsl,qe",
 503                                 "fsl,qe-num-snums", 76, 1);
 504         }
 505 }
 506 #endif
 507
 508 #if defined(CONFIG_ARCH_P4080)
 509 static void fdt_fixup_usb(void *fdt)
 510 {
 511         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 512         u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 513         int off;
 514
 515         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
 516         if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
 517                                 FSL_CORENET_RCWSR11_EC1_FM1_USB1)
 518                 fdt_status_disabled(fdt, off);
 519
 520         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
 521         if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
 522                                 FSL_CORENET_RCWSR11_EC2_USB2)
 523                 fdt_status_disabled(fdt, off);
 524 }
 525 #else
 526 #define fdt_fixup_usb(x)
 527 #endif
 528
 529 #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
 530         defined(CONFIG_ARCH_T4160)
 531 void fdt_fixup_dma3(void *blob)
 532 {
 533         /* the 3rd DMA is not functional if SRIO2 is chosen */
 534         int nodeoff;
 535         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 536
 537 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
 538 #if defined(CONFIG_ARCH_T2080)
 539         u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 540                                     FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 541         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 542
 543         switch (srds_prtcl_s2) {
 544         case 0x29:
 545         case 0x2d:
 546         case 0x2e:
 547 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
 548         u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
 549                                     FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
 550         srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
 551
 552         switch (srds_prtcl_s4) {
 553         case 6:
 554         case 8:
 555         case 14:
 556         case 16:
 557 #endif
 558                 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
 559                                                         CONFIG_SYS_ELO3_DMA3);
 560                 if (nodeoff > 0)
 561                         fdt_status_disabled(blob, nodeoff);
 562                 else
 563                         printf("WARNING: unable to disable dma3\n");
 564                 break;
 565         default:
 566                 break;
 567         }
 568 }
 569 #else
 570 #define fdt_fixup_dma3(x)
 571 #endif
 572
 573 #if defined(CONFIG_ARCH_T1040)
 574 static void fdt_fixup_l2_switch(void *blob)
 575 {
 576         uchar l2swaddr[6];
 577         int node;
 578
 579         /* The l2switch node from device-tree has
 580          * compatible string "vitesse-9953" */
 581         node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
 582         if (node == -FDT_ERR_NOTFOUND)
 583                 /* no l2switch node has been found */
 584                 return;
 585
 586         /* Get MAC address for the l2switch from "l2switchaddr"*/
 587         if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
 588                 printf("Warning: MAC address for l2switch not found\n");
 589                 memset(l2swaddr, 0, sizeof(l2swaddr));
 590         }
 591
 592         /* Add MAC address to l2switch node */
 593         fdt_setprop(blob, node, "local-mac-address", l2swaddr,
 594                     sizeof(l2swaddr));
 595 }
 596 #else
 597 #define fdt_fixup_l2_switch(x)
 598 #endif
 599
 600 void ft_cpu_setup(void *blob, bd_t *bd)
 601 {
 602         int off;
 603         int val;
 604         int len;
 605         sys_info_t sysinfo;
 606
 607         /* delete crypto node if not on an E-processor */
 608         if (!IS_E_PROCESSOR(get_svr()))
 609                 fdt_fixup_crypto_node(blob, 0);
 610 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
 611         else {
 612                 ccsr_sec_t __iomem *sec;
 613
 614                 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
 615                 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 616         }
 617 #endif
 618
 619         fdt_add_enet_stashing(blob);
 620
 621 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
 622 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
 623 #endif
 624         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 625                 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
 626                 1);
 627         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 628                 "bus-frequency", bd->bi_busfreq, 1);
 629         get_sys_info(&sysinfo);
 630         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 631         while (off != -FDT_ERR_NOTFOUND) {
 632                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
 633                 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
 634                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 635                 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
 636                                                         "cpu", 4);
 637         }
 638         do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 639                 "bus-frequency", bd->bi_busfreq, 1);
 640
 641 #ifdef CONFIG_QE
 642         ft_qe_setup(blob);
 643         ft_fixup_qe_snum(blob);
 644 #endif
 645
 646 #ifdef CONFIG_SYS_DPAA_FMAN
 647         fdt_fixup_fman_firmware(blob);
 648 #endif
 649
 650 #ifdef CONFIG_SYS_NS16550
 651         do_fixup_by_compat_u32(blob, "ns16550",
 652                 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 653 #endif
 654
 655 #ifdef CONFIG_CPM2
 656         do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
 657                 "current-speed", gd->baudrate, 1);
 658
 659         do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 660                 "clock-frequency", bd->bi_brgfreq, 1);
 661 #endif
 662
 663 #ifdef CONFIG_FSL_CORENET
 664         do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
 665                 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 666         do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
 667                 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 668         do_fixup_by_compat_u32(blob, "fsl,mpic",
 669                 "clock-frequency", get_bus_freq(0)/2, 1);
 670 #else
 671         do_fixup_by_compat_u32(blob, "fsl,mpic",
 672                 "clock-frequency", get_bus_freq(0), 1);
 673 #endif
 674
 675         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 676
 677 #ifdef CONFIG_MP
 678         ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
 679         ft_fixup_num_cores(blob);
 680 #endif
 681
 682         ft_fixup_cache(blob);
 683
 684 #if defined(CONFIG_FSL_ESDHC)
 685         fdt_fixup_esdhc(blob, bd);
 686 #endif
 687
 688         ft_fixup_dpaa_clks(blob);
 689
 690 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
 691         fdt_portal(blob, "fsl,bman-portal", "bman-portals",
 692                         (u64)CONFIG_SYS_BMAN_MEM_PHYS,
 693                         CONFIG_SYS_BMAN_MEM_SIZE);
 694         fdt_fixup_bportals(blob);
 695 #endif
 696
 697 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
 698         fdt_portal(blob, "fsl,qman-portal", "qman-portals",
 699                         (u64)CONFIG_SYS_QMAN_MEM_PHYS,
 700                         CONFIG_SYS_QMAN_MEM_SIZE);
 701
 702         fdt_fixup_qportals(blob);
 703 #endif
 704
 705 #ifdef CONFIG_SYS_SRIO
 706         ft_srio_setup(blob);
 707 #endif
 708
 709         /*
 710          * system-clock = CCB clock/2
 711          * Here gd->bus_clk = CCB clock
 712          * We are using the system clock as 1588 Timer reference
 713          * clock source select
 714          */
 715         do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
 716                         "timer-frequency", gd->bus_clk/2, 1);
 717
 718         /*
 719          * clock-freq should change to clock-frequency and
 720          * flexcan-v1.0 should change to p1010-flexcan respectively
 721          * in the future.
 722          */
 723         do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
 724                         "clock_freq", gd->bus_clk/2, 1);
 725
 726         do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
 727                         "clock-frequency", gd->bus_clk/2, 1);
 728
 729         do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
 730                         "clock-frequency", gd->bus_clk/2, 1);
 731
 732         fdt_fixup_usb(blob);
 733
 734         fdt_fixup_l2_switch(blob);
 735
 736         fdt_fixup_dma3(blob);
 737 }
 738
 739 /*
 740  * For some CCSR devices, we only have the virtual address, not the physical
 741  * address.  This is because we map CCSR as a whole, so we typically don't need
 742  * a macro for the physical address of any device within CCSR.  In this case,
 743  * we calculate the physical address of that device using it's the difference
 744  * between the virtual address of the device and the virtual address of the
 745  * beginning of CCSR.
 746  */
 747 #define CCSR_VIRT_TO_PHYS(x) \
 748         (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
 749
 750 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
 751 {
 752         printf("Warning: U-Boot configured %s at address %llx,\n"
 753                "but the device tree has it at %llx\n", name, uaddr, daddr);
 754 }
 755
 756 /*
 757  * Verify the device tree
 758  *
 759  * This function compares several CONFIG_xxx macros that contain physical
 760  * addresses with the corresponding nodes in the device tree, to see if
 761  * the physical addresses are all correct.  For example, if
 762  * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
 763  * of the first UART.  We convert this to a physical address and compare
 764  * that with the physical address of the first ns16550-compatible node
 765  * in the device tree.  If they don't match, then we display a warning.
 766  *
 767  * Returns 1 on success, 0 on failure
 768  */
 769 int ft_verify_fdt(void *fdt)
 770 {
 771         uint64_t addr = 0;
 772         int aliases;
 773         int off;
 774
 775         /* First check the CCSR base address */
 776         off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
 777         if (off > 0) {
 778                 int size;
 779                 u32 naddr;
 780                 const fdt32_t *prop;
 781
 782                 naddr = fdt_address_cells(fdt, off);
 783                 prop = fdt_getprop(fdt, off, "ranges", &size);
 784                 addr = fdt_translate_address(fdt, off, prop + naddr);
 785         }
 786
 787         if (!addr) {
 788                 printf("Warning: could not determine base CCSR address in "
 789                        "device tree\n");
 790                 /* No point in checking anything else */
 791                 return 0;
 792         }
 793
 794         if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
 795                 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
 796                 /* No point in checking anything else */
 797                 return 0;
 798         }
 799
 800         /*
 801          * Check some nodes via aliases.  We assume that U-Boot and the device
 802          * tree enumerate the devices equally.  E.g. the first serial port in
 803          * U-Boot is the same as "serial0" in the device tree.
 804          */
 805         aliases = fdt_path_offset(fdt, "/aliases");
 806         if (aliases > 0) {
 807 #ifdef CONFIG_SYS_NS16550_COM1
 808                 if (!fdt_verify_alias_address(fdt, aliases, "serial0",
 809                         CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
 810                         return 0;
 811 #endif
 812
 813 #ifdef CONFIG_SYS_NS16550_COM2
 814                 if (!fdt_verify_alias_address(fdt, aliases, "serial1",
 815                         CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
 816                         return 0;
 817 #endif
 818         }
 819
 820         /*
 821          * The localbus node is typically a root node, even though the lbc
 822          * controller is part of CCSR.  If we were to put the lbc node under
 823          * the SOC node, then the 'ranges' property in the lbc node would
 824          * translate through the 'ranges' property of the parent SOC node, and
 825          * we don't want that.  Since it's a separate node, it's possible for
 826          * the 'reg' property to be wrong, so check it here.  For now, we
 827          * only check for "fsl,elbc" nodes.
 828          */
 829 #ifdef CONFIG_SYS_LBC_ADDR
 830         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
 831         if (off > 0) {
 832                 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
 833                 if (reg) {
 834                         uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
 835
 836                         addr = fdt_translate_address(fdt, off, reg);
 837                         if (uaddr != addr) {
 838                                 msg("the localbus", uaddr, addr);
 839                                 return 0;
 840                         }
 841                 }
 842         }
 843 #endif
 844
 845         return 1;
 846 }
 847
 848 void fdt_del_diu(void *blob)
 849 {
 850         int nodeoff = 0;
 851
 852         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 853                                 "fsl,diu")) >= 0) {
 854                 fdt_del_node(blob, nodeoff);
 855         }
 856 }