arch/powerpc/cpu/mpc85xx/cpu_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2003 Motorola Inc.
   6  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   7  *
   8  * (C) Copyright 2000
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  */
  11
  12 #include <common.h>
  13 #include <env.h>
  14 #include <init.h>
  15 #include <net.h>
  16 #include <watchdog.h>
  17 #include <asm/processor.h>
  18 #include <ioports.h>
  19 #include <sata.h>
  20 #include <fm_eth.h>
  21 #include <asm/io.h>
  22 #include <asm/cache.h>
  23 #include <asm/mmu.h>
  24 #include <fsl_errata.h>
  25 #include <asm/fsl_law.h>
  26 #include <asm/fsl_serdes.h>
  27 #include <asm/fsl_srio.h>
  28 #ifdef CONFIG_FSL_CORENET
  29 #include <asm/fsl_portals.h>
  30 #include <asm/fsl_liodn.h>
  31 #include <fsl_qbman.h>
  32 #endif
  33 #include <fsl_usb.h>
  34 #include <hwconfig.h>
  35 #include <linux/compiler.h>
  36 #include "mp.h"
  37 #ifdef CONFIG_CHAIN_OF_TRUST
  38 #include <fsl_validate.h>
  39 #endif
  40 #ifdef CONFIG_FSL_CAAM
  41 #include <fsl_sec.h>
  42 #endif
  43 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
  44 #include <asm/fsl_pamu.h>
  45 #include <fsl_secboot_err.h>
  46 #endif
  47 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
  48 #include <nand.h>
  49 #include <errno.h>
  50 #endif
  51 #ifndef CONFIG_ARCH_QEMU_E500
  52 #include <fsl_ddr.h>
  53 #endif
  54 #include "../../../../drivers/ata/fsl_sata.h"
  55 #ifdef CONFIG_U_QE
  56 #include <fsl_qe.h>
  57 #endif
  58
  59 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  60 /*
  61  * For deriving usb clock from 100MHz sysclk, reference divisor is set
  62  * to a value of 5, which gives an intermediate value 20(100/5). The
  63  * multiplication factor integer is set to 24, which when multiplied to
  64  * above intermediate value provides clock for usb ip.
  65  */
  66 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
  67 {
  68         sys_info_t sysinfo;
  69
  70         get_sys_info(&sysinfo);
  71         if (sysinfo.diff_sysclk == 1) {
  72                 clrbits_be32(&usb_phy->pllprg[1],
  73                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
  74                 setbits_be32(&usb_phy->pllprg[1],
  75                              CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
  76                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
  77                              CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
  78                 }
  79 }
  80 #endif
  81
  82 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  83 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
  84 {
  85 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  86         u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
  87
  88         /* Increase Disconnect Threshold by 50mV */
  89         xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  90                                                 INC_DCNT_THRESHOLD_50MV;
  91         /* Enable programming of USB High speed Disconnect threshold */
  92         xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  93         out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
  94
  95         xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
  96         /* Increase Disconnect Threshold by 50mV */
  97         xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  98                                                 INC_DCNT_THRESHOLD_50MV;
  99         /* Enable programming of USB High speed Disconnect threshold */
 100         xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
 101         out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
 102 #else
 103
 104         u32 temp = 0;
 105         u32 status = in_be32(&usb_phy->status1);
 106
 107         u32 squelch_prog_rd_0_2 =
 108                 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
 109                         & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
 110
 111         u32 squelch_prog_rd_3_5 =
 112                 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
 113                         & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
 114
 115         setbits_be32(&usb_phy->config1,
 116                      CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
 117         setbits_be32(&usb_phy->config2,
 118                      CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
 119
 120         temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
 121         out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
 122
 123         temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
 124         out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
 125 #endif
 126 }
 127 #endif
 128
 129
 130 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
 131 extern qe_iop_conf_t qe_iop_conf_tab[];
 132 extern void qe_config_iopin(u8 port, u8 pin, int dir,
 133                                 int open_drain, int assign);
 134 extern void qe_init(uint qe_base);
 135 extern void qe_reset(void);
 136
 137 static void config_qe_ioports(void)
 138 {
 139         u8      port, pin;
 140         int     dir, open_drain, assign;
 141         int     i;
 142
 143         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
 144                 port            = qe_iop_conf_tab[i].port;
 145                 pin             = qe_iop_conf_tab[i].pin;
 146                 dir             = qe_iop_conf_tab[i].dir;
 147                 open_drain      = qe_iop_conf_tab[i].open_drain;
 148                 assign          = qe_iop_conf_tab[i].assign;
 149                 qe_config_iopin(port, pin, dir, open_drain, assign);
 150         }
 151 }
 152 #endif
 153
 154 #ifdef CONFIG_CPM2
 155 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 156 {
 157         int portnum;
 158
 159         for (portnum = 0; portnum < 4; portnum++) {
 160                 uint pmsk = 0,
 161                      ppar = 0,
 162                      psor = 0,
 163                      pdir = 0,
 164                      podr = 0,
 165                      pdat = 0;
 166                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
 167                 iop_conf_t *eiopc = iopc + 32;
 168                 uint msk = 1;
 169
 170                 /*
 171                  * NOTE:
 172                  * index 0 refers to pin 31,
 173                  * index 31 refers to pin 0
 174                  */
 175                 while (iopc < eiopc) {
 176                         if (iopc->conf) {
 177                                 pmsk |= msk;
 178                                 if (iopc->ppar)
 179                                         ppar |= msk;
 180                                 if (iopc->psor)
 181                                         psor |= msk;
 182                                 if (iopc->pdir)
 183                                         pdir |= msk;
 184                                 if (iopc->podr)
 185                                         podr |= msk;
 186                                 if (iopc->pdat)
 187                                         pdat |= msk;
 188                         }
 189
 190                         msk <<= 1;
 191                         iopc++;
 192                 }
 193
 194                 if (pmsk != 0) {
 195                         volatile ioport_t *iop = ioport_addr (cpm, portnum);
 196                         uint tpmsk = ~pmsk;
 197
 198                         /*
 199                          * the (somewhat confused) paragraph at the
 200                          * bottom of page 35-5 warns that there might
 201                          * be "unknown behaviour" when programming
 202                          * PSORx and PDIRx, if PPARx = 1, so I
 203                          * decided this meant I had to disable the
 204                          * dedicated function first, and enable it
 205                          * last.
 206                          */
 207                         iop->ppar &= tpmsk;
 208                         iop->psor = (iop->psor & tpmsk) | psor;
 209                         iop->podr = (iop->podr & tpmsk) | podr;
 210                         iop->pdat = (iop->pdat & tpmsk) | pdat;
 211                         iop->pdir = (iop->pdir & tpmsk) | pdir;
 212                         iop->ppar |= ppar;
 213                 }
 214         }
 215 }
 216 #endif
 217
 218 #ifdef CONFIG_SYS_FSL_CPC
 219 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
 220 void disable_cpc_sram(void)
 221 {
 222         int i;
 223
 224         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 225
 226         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 227                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
 228                         /* find and disable LAW of SRAM */
 229                         struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
 230
 231                         if (law.index == -1) {
 232                                 printf("\nFatal error happened\n");
 233                                 return;
 234                         }
 235                         disable_law(law.index);
 236
 237                         clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
 238                         out_be32(&cpc->cpccsr0, 0);
 239                         out_be32(&cpc->cpcsrcr0, 0);
 240                 }
 241         }
 242 }
 243 #endif
 244
 245 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
 246 #ifdef CONFIG_POST
 247 #error POST memory test cannot be enabled with TDM
 248 #endif
 249 static void enable_tdm_law(void)
 250 {
 251         int ret;
 252         char buffer[HWCONFIG_BUFFER_SIZE] = {0};
 253         int tdm_hwconfig_enabled = 0;
 254
 255         /*
 256          * Extract hwconfig from environment since environment
 257          * is not setup properly yet. Search for tdm entry in
 258          * hwconfig.
 259          */
 260         ret = env_get_f("hwconfig", buffer, sizeof(buffer));
 261         if (ret > 0) {
 262                 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
 263                 /* If tdm is defined in hwconfig, set law for tdm workaround */
 264                 if (tdm_hwconfig_enabled)
 265                         set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
 266                                      LAW_TRGT_IF_CCSR);
 267         }
 268 }
 269 #endif
 270
 271 void enable_cpc(void)
 272 {
 273         int i;
 274         int ret;
 275         u32 size = 0;
 276         u32 cpccfg0;
 277         char buffer[HWCONFIG_BUFFER_SIZE];
 278         char cpc_subarg[16];
 279         bool have_hwconfig = false;
 280         int cpc_args = 0;
 281         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 282
 283         /* Extract hwconfig from environment */
 284         ret = env_get_f("hwconfig", buffer, sizeof(buffer));
 285         if (ret > 0) {
 286                 /*
 287                  * If "en_cpc" is not defined in hwconfig then by default all
 288                  * cpcs are enable. If this config is defined then individual
 289                  * cpcs which have to be enabled should also be defined.
 290                  * e.g en_cpc:cpc1,cpc2;
 291                  */
 292                 if (hwconfig_f("en_cpc", buffer))
 293                         have_hwconfig = true;
 294         }
 295
 296         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 297                 if (have_hwconfig) {
 298                         sprintf(cpc_subarg, "cpc%u", i + 1);
 299                         cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
 300                         if (cpc_args == 0)
 301                                 continue;
 302                 }
 303                 cpccfg0 = in_be32(&cpc->cpccfg0);
 304                 size += CPC_CFG0_SZ_K(cpccfg0);
 305
 306 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
 307                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
 308 #endif
 309 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
 310                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
 311 #endif
 312 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 313                 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
 314 #endif
 315 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
 316                 if (has_erratum_a006379()) {
 317                         setbits_be32(&cpc->cpchdbcr0,
 318                                      CPC_HDBCR0_SPLRU_LEVEL_EN);
 319                 }
 320 #endif
 321
 322                 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 323                 /* Read back to sync write */
 324                 in_be32(&cpc->cpccsr0);
 325
 326         }
 327
 328         puts("Corenet Platform Cache: ");
 329         print_size(size * 1024, " enabled\n");
 330 }
 331
 332 static void invalidate_cpc(void)
 333 {
 334         int i;
 335         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 336
 337         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 338                 /* skip CPC when it used as all SRAM */
 339                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
 340                         continue;
 341                 /* Flash invalidate the CPC and clear all the locks */
 342                 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
 343                 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
 344                         ;
 345         }
 346 }
 347 #else
 348 #define enable_cpc()
 349 #define invalidate_cpc()
 350 #define disable_cpc_sram()
 351 #endif /* CONFIG_SYS_FSL_CPC */
 352
 353 /*
 354  * Breathe some life into the CPU...
 355  *
 356  * Set up the memory map
 357  * initialize a bunch of registers
 358  */
 359
 360 #ifdef CONFIG_FSL_CORENET
 361 static void corenet_tb_init(void)
 362 {
 363         volatile ccsr_rcpm_t *rcpm =
 364                 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 365         volatile ccsr_pic_t *pic =
 366                 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 367         u32 whoami = in_be32(&pic->whoami);
 368
 369         /* Enable the timebase register for this core */
 370         out_be32(&rcpm->ctbenrl, (1 << whoami));
 371 }
 372 #endif
 373
 374 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 375 void fsl_erratum_a007212_workaround(void)
 376 {
 377         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 378         u32 ddr_pll_ratio;
 379         u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
 380         u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
 381         u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
 382 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 383         u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
 384         u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
 385 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
 386         u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
 387         u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
 388 #endif
 389 #endif
 390         /*
 391          * Even this workaround applies to selected version of SoCs, it is
 392          * safe to apply to all versions, with the limitation of odd ratios.
 393          * If RCW has disabled DDR PLL, we have to apply this workaround,
 394          * otherwise DDR will not work.
 395          */
 396         ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
 397                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
 398                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 399         /* check if RCW sets ratio to 0, required by this workaround */
 400         if (ddr_pll_ratio != 0)
 401                 return;
 402         ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
 403                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
 404                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 405         /* check if reserved bits have the desired ratio */
 406         if (ddr_pll_ratio == 0) {
 407                 printf("Error: Unknown DDR PLL ratio!\n");
 408                 return;
 409         }
 410         ddr_pll_ratio >>= 1;
 411
 412         setbits_be32(plldadcr1, 0x02000001);
 413 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 414         setbits_be32(plldadcr2, 0x02000001);
 415 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
 416         setbits_be32(plldadcr3, 0x02000001);
 417 #endif
 418 #endif
 419         setbits_be32(dpdovrcr4, 0xe0000000);
 420         out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
 421 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 422         out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
 423 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
 424         out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
 425 #endif
 426 #endif
 427         udelay(100);
 428         clrbits_be32(plldadcr1, 0x02000001);
 429 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 430         clrbits_be32(plldadcr2, 0x02000001);
 431 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
 432         clrbits_be32(plldadcr3, 0x02000001);
 433 #endif
 434 #endif
 435         clrbits_be32(dpdovrcr4, 0xe0000000);
 436 }
 437 #endif
 438
 439 ulong cpu_init_f(void)
 440 {
 441         extern void m8560_cpm_reset (void);
 442 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 443         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 444 #endif
 445 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
 446         struct law_entry law;
 447 #endif
 448 #ifdef CONFIG_ARCH_MPC8548
 449         ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 450         uint svr = get_svr();
 451
 452         /*
 453          * CPU2 errata workaround: A core hang possible while executing
 454          * a msync instruction and a snoopable transaction from an I/O
 455          * master tagged to make quick forward progress is present.
 456          * Fixed in silicon rev 2.1.
 457          */
 458         if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
 459                 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 460 #endif
 461
 462         disable_tlb(14);
 463         disable_tlb(15);
 464
 465 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
 466         /* Disable the LAW created for NOR flash by the PBI commands */
 467         law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
 468         if (law.index != -1)
 469                 disable_law(law.index);
 470
 471 #if defined(CONFIG_SYS_CPC_REINIT_F)
 472         disable_cpc_sram();
 473 #endif
 474 #endif
 475
 476 #ifdef CONFIG_CPM2
 477         config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 478 #endif
 479
 480        init_early_memctl_regs();
 481
 482 #if defined(CONFIG_CPM2)
 483         m8560_cpm_reset();
 484 #endif
 485
 486 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
 487         /* Config QE ioports */
 488         config_qe_ioports();
 489 #endif
 490
 491 #if defined(CONFIG_FSL_DMA)
 492         dma_init();
 493 #endif
 494 #ifdef CONFIG_FSL_CORENET
 495         corenet_tb_init();
 496 #endif
 497         init_used_tlb_cams();
 498
 499         /* Invalidate the CPC before DDR gets enabled */
 500         invalidate_cpc();
 501
 502  #ifdef CONFIG_SYS_DCSRBAR_PHYS
 503         /* set DCSRCR so that DCSR space is 1G */
 504         setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
 505         in_be32(&gur->dcsrcr);
 506 #endif
 507
 508 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 509         fsl_erratum_a007212_workaround();
 510 #endif
 511
 512         return 0;
 513 }
 514
 515 /* Implement a dummy function for those platforms w/o SERDES */
 516 static void __fsl_serdes__init(void)
 517 {
 518         return ;
 519 }
 520 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 521
 522 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 523 int enable_cluster_l2(void)
 524 {
 525         int i = 0;
 526         u32 cluster, svr = get_svr();
 527         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 528         struct ccsr_cluster_l2 __iomem *l2cache;
 529
 530         /* only the L2 of first cluster should be enabled as expected on T4080,
 531          * but there is no EOC in the first cluster as HW sake, so return here
 532          * to skip enabling L2 cache of the 2nd cluster.
 533          */
 534         if (SVR_SOC_VER(svr) == SVR_T4080)
 535                 return 0;
 536
 537         cluster = in_be32(&gur->tp_cluster[i].lower);
 538         if (cluster & TP_CLUSTER_EOC)
 539                 return 0;
 540
 541         /* The first cache has already been set up, so skip it */
 542         i++;
 543
 544         /* Look through the remaining clusters, and set up their caches */
 545         do {
 546                 int j, cluster_valid = 0;
 547
 548                 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
 549
 550                 cluster = in_be32(&gur->tp_cluster[i].lower);
 551
 552                 /* check that at least one core/accel is enabled in cluster */
 553                 for (j = 0; j < 4; j++) {
 554                         u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
 555                         u32 type = in_be32(&gur->tp_ityp[idx]);
 556
 557                         if ((type & TP_ITYP_AV) &&
 558                             TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
 559                                 cluster_valid = 1;
 560                 }
 561
 562                 if (cluster_valid) {
 563                         /* set stash ID to (cluster) * 2 + 32 + 1 */
 564                         clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
 565
 566                         printf("enable l2 for cluster %d %p\n", i, l2cache);
 567
 568                         out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
 569                         while ((in_be32(&l2cache->l2csr0)
 570                                 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
 571                                         ;
 572                         out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
 573                 }
 574                 i++;
 575         } while (!(cluster & TP_CLUSTER_EOC));
 576
 577         return 0;
 578 }
 579 #endif
 580
 581 /*
 582  * Initialize L2 as cache.
 583  */
 584 int l2cache_init(void)
 585 {
 586         __maybe_unused u32 svr = get_svr();
 587 #ifdef CONFIG_L2_CACHE
 588         ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
 589 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 590         struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 591 #endif
 592
 593         puts ("L2:    ");
 594
 595 #if defined(CONFIG_L2_CACHE)
 596         volatile uint cache_ctl;
 597         uint ver;
 598         u32 l2siz_field;
 599
 600         ver = SVR_SOC_VER(svr);
 601
 602         asm("msync;isync");
 603         cache_ctl = l2cache->l2ctl;
 604
 605 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 606         if (cache_ctl & MPC85xx_L2CTL_L2E) {
 607                 /* Clear L2 SRAM memory-mapped base address */
 608                 out_be32(&l2cache->l2srbar0, 0x0);
 609                 out_be32(&l2cache->l2srbar1, 0x0);
 610
 611                 /* set MBECCDIS=0, SBECCDIS=0 */
 612                 clrbits_be32(&l2cache->l2errdis,
 613                                 (MPC85xx_L2ERRDIS_MBECC |
 614                                  MPC85xx_L2ERRDIS_SBECC));
 615
 616                 /* set L2E=0, L2SRAM=0 */
 617                 clrbits_be32(&l2cache->l2ctl,
 618                                 (MPC85xx_L2CTL_L2E |
 619                                  MPC85xx_L2CTL_L2SRAM_ENTIRE));
 620         }
 621 #endif
 622
 623         l2siz_field = (cache_ctl >> 28) & 0x3;
 624
 625         switch (l2siz_field) {
 626         case 0x0:
 627                 printf(" unknown size (0x%08x)\n", cache_ctl);
 628                 return -1;
 629                 break;
 630         case 0x1:
 631                 if (ver == SVR_8540 || ver == SVR_8560   ||
 632                     ver == SVR_8541 || ver == SVR_8555) {
 633                         puts("128 KiB ");
 634                         /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
 635                         cache_ctl = 0xc4000000;
 636                 } else {
 637                         puts("256 KiB ");
 638                         cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 639                 }
 640                 break;
 641         case 0x2:
 642                 if (ver == SVR_8540 || ver == SVR_8560   ||
 643                     ver == SVR_8541 || ver == SVR_8555) {
 644                         puts("256 KiB ");
 645                         /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
 646                         cache_ctl = 0xc8000000;
 647                 } else {
 648                         puts("512 KiB ");
 649                         /* set L2E=1, L2I=1, & L2SRAM=0 */
 650                         cache_ctl = 0xc0000000;
 651                 }
 652                 break;
 653         case 0x3:
 654                 puts("1024 KiB ");
 655                 /* set L2E=1, L2I=1, & L2SRAM=0 */
 656                 cache_ctl = 0xc0000000;
 657                 break;
 658         }
 659
 660         if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 661                 puts("already enabled");
 662 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
 663                 u32 l2srbar = l2cache->l2srbar0;
 664                 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 665                                 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
 666                         l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 667                         l2cache->l2srbar0 = l2srbar;
 668                         printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 669                 }
 670 #endif /* CONFIG_SYS_INIT_L2_ADDR */
 671                 puts("\n");
 672         } else {
 673                 asm("msync;isync");
 674                 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 675                 asm("msync;isync");
 676                 puts("enabled\n");
 677         }
 678 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 679         if (SVR_SOC_VER(svr) == SVR_P2040) {
 680                 puts("N/A\n");
 681                 goto skip_l2;
 682         }
 683
 684         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 685
 686         /* invalidate the L2 cache */
 687         mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
 688         while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
 689                 ;
 690
 691 #ifdef CONFIG_SYS_CACHE_STASHING
 692         /* set stash id to (coreID) * 2 + 32 + L2 (1) */
 693         mtspr(SPRN_L2CSR1, (32 + 1));
 694 #endif
 695
 696         /* enable the cache */
 697         mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 698
 699         if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
 700                 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
 701                         ;
 702                 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
 703         }
 704
 705 skip_l2:
 706 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 707         if (l2cache->l2csr0 & L2CSR0_L2E)
 708                 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
 709                            " enabled\n");
 710
 711         enable_cluster_l2();
 712 #else
 713         puts("disabled\n");
 714 #endif
 715
 716         return 0;
 717 }
 718
 719 /*
 720  *
 721  * The newer 8548, etc, parts have twice as much cache, but
 722  * use the same bit-encoding as the older 8555, etc, parts.
 723  *
 724  */
 725 int cpu_init_r(void)
 726 {
 727         __maybe_unused u32 svr = get_svr();
 728 #ifdef CONFIG_SYS_LBC_LCRR
 729         fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
 730 #endif
 731 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
 732         extern int spin_table_compat;
 733         const char *spin;
 734 #endif
 735 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 736         ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
 737 #endif
 738 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 739         defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 740         /*
 741          * CPU22 and NMG_CPU_A011 share the same workaround.
 742          * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 743          * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 744          * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
 745          * fixed in 2.0. NMG_CPU_A011 is activated by default and can
 746          * be disabled by hwconfig with syntax:
 747          *
 748          * fsl_cpu_a011:disable
 749          */
 750         extern int enable_cpu_a011_workaround;
 751 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
 752         enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
 753 #else
 754         char buffer[HWCONFIG_BUFFER_SIZE];
 755         char *buf = NULL;
 756         int n, res;
 757
 758         n = env_get_f("hwconfig", buffer, sizeof(buffer));
 759         if (n > 0)
 760                 buf = buffer;
 761
 762         res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
 763         if (res > 0) {
 764                 enable_cpu_a011_workaround = 0;
 765         } else {
 766                 if (n >= HWCONFIG_BUFFER_SIZE) {
 767                         printf("fsl_cpu_a011 was not found. hwconfig variable "
 768                                 "may be too long\n");
 769                 }
 770                 enable_cpu_a011_workaround =
 771                         (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
 772                         (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
 773         }
 774 #endif
 775         if (enable_cpu_a011_workaround) {
 776                 flush_dcache();
 777                 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
 778                 sync();
 779         }
 780 #endif
 781
 782 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
 783         flush_dcache();
 784         mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
 785         sync();
 786 #endif
 787
 788 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
 789         /*
 790          * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
 791          * in write shadow mode. Checking DCWS before setting SPR 976.
 792          */
 793         if (mfspr(L1CSR2) & L1CSR2_DCWS)
 794                 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
 795 #endif
 796
 797 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
 798         spin = env_get("spin_table_compat");
 799         if (spin && (*spin == 'n'))
 800                 spin_table_compat = 0;
 801         else
 802                 spin_table_compat = 1;
 803 #endif
 804
 805 #ifdef CONFIG_FSL_CORENET
 806         set_liodns();
 807 #ifdef CONFIG_SYS_DPAA_QBMAN
 808         setup_qbman_portals();
 809 #endif
 810 #endif
 811
 812         l2cache_init();
 813 #if defined(CONFIG_RAMBOOT_PBL)
 814         disable_cpc_sram();
 815 #endif
 816         enable_cpc();
 817 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
 818         enable_tdm_law();
 819 #endif
 820
 821 #ifndef CONFIG_SYS_FSL_NO_SERDES
 822         /* needs to be in ram since code uses global static vars */
 823         fsl_serdes_init();
 824 #endif
 825
 826 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 827 #define MCFGR_AXIPIPE 0x000000f0
 828         if (IS_SVR_REV(svr, 1, 0))
 829                 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
 830 #endif
 831
 832 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
 833         if (IS_SVR_REV(svr, 1, 0)) {
 834                 int i;
 835                 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
 836
 837                 for (i = 0; i < 12; i++) {
 838                         p += i + (i > 5 ? 11 : 0);
 839                         out_be32(p, 0x2);
 840                 }
 841                 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
 842                 out_be32(p, 0x34);
 843         }
 844 #endif
 845
 846 #ifdef CONFIG_SYS_SRIO
 847         srio_init();
 848 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 849         char *s = env_get("bootmaster");
 850         if (s) {
 851                 if (!strcmp(s, "SRIO1")) {
 852                         srio_boot_master(1);
 853                         srio_boot_master_release_slave(1);
 854                 }
 855                 if (!strcmp(s, "SRIO2")) {
 856                         srio_boot_master(2);
 857                         srio_boot_master_release_slave(2);
 858                 }
 859         }
 860 #endif
 861 #endif
 862
 863 #if defined(CONFIG_MP)
 864         setup_mp();
 865 #endif
 866
 867 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
 868         {
 869                 if (SVR_MAJ(svr) < 3) {
 870                         void *p;
 871                         p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
 872                         setbits_be32(p, 1 << (31 - 14));
 873                 }
 874         }
 875 #endif
 876
 877 #ifdef CONFIG_SYS_LBC_LCRR
 878         /*
 879          * Modify the CLKDIV field of LCRR register to improve the writing
 880          * speed for NOR flash.
 881          */
 882         clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
 883         __raw_readl(&lbc->lcrr);
 884         isync();
 885 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 886         udelay(100);
 887 #endif
 888 #endif
 889
 890 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 891         {
 892                 struct ccsr_usb_phy __iomem *usb_phy1 =
 893                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 894 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 895                 if (has_erratum_a006261())
 896                         fsl_erratum_a006261_workaround(usb_phy1);
 897 #endif
 898                 out_be32(&usb_phy1->usb_enable_override,
 899                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 900         }
 901 #endif
 902 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 903         {
 904                 struct ccsr_usb_phy __iomem *usb_phy2 =
 905                         (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
 906 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 907                 if (has_erratum_a006261())
 908                         fsl_erratum_a006261_workaround(usb_phy2);
 909 #endif
 910                 out_be32(&usb_phy2->usb_enable_override,
 911                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 912         }
 913 #endif
 914
 915 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
 916         /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
 917          * multi-bit ECC errors which has impact on performance, so software
 918          * should disable all ECC reporting from USB1 and USB2.
 919          */
 920         if (IS_SVR_REV(get_svr(), 1, 0)) {
 921                 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
 922                         (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
 923                 setbits_be32(&dcfg->ecccr1,
 924                                 (DCSR_DCFG_ECC_DISABLE_USB1 |
 925                                  DCSR_DCFG_ECC_DISABLE_USB2));
 926         }
 927 #endif
 928
 929 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
 930                 struct ccsr_usb_phy __iomem *usb_phy =
 931                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 932                 setbits_be32(&usb_phy->pllprg[1],
 933                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
 934                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
 935                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
 936                              CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
 937 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 938                 usb_single_source_clk_configure(usb_phy);
 939 #endif
 940                 setbits_be32(&usb_phy->port1.ctrl,
 941                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 942                 setbits_be32(&usb_phy->port1.drvvbuscfg,
 943                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 944                 setbits_be32(&usb_phy->port1.pwrfltcfg,
 945                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 946                 setbits_be32(&usb_phy->port2.ctrl,
 947                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 948                 setbits_be32(&usb_phy->port2.drvvbuscfg,
 949                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 950                 setbits_be32(&usb_phy->port2.pwrfltcfg,
 951                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 952
 953 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 954                 if (has_erratum_a006261())
 955                         fsl_erratum_a006261_workaround(usb_phy);
 956 #endif
 957
 958 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
 959
 960 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 961         erratum_a009942_check_cpo();
 962 #endif
 963
 964 #ifdef CONFIG_FMAN_ENET
 965         fman_enet_init();
 966 #endif
 967
 968 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
 969         if (pamu_init() < 0)
 970                 fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
 971 #endif
 972
 973 #ifdef CONFIG_FSL_CAAM
 974         sec_init();
 975
 976 #if defined(CONFIG_ARCH_C29X)
 977         if ((SVR_SOC_VER(svr) == SVR_C292) ||
 978             (SVR_SOC_VER(svr) == SVR_C293))
 979                 sec_init_idx(1);
 980
 981         if (SVR_SOC_VER(svr) == SVR_C293)
 982                 sec_init_idx(2);
 983 #endif
 984 #endif
 985
 986 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
 987         /*
 988          * For P1022/1013 Rev1.0 silicon, after power on SATA host
 989          * controller is configured in legacy mode instead of the
 990          * expected enterprise mode. Software needs to clear bit[28]
 991          * of HControl register to change to enterprise mode from
 992          * legacy mode.  We assume that the controller is offline.
 993          */
 994         if (IS_SVR_REV(svr, 1, 0) &&
 995             ((SVR_SOC_VER(svr) == SVR_P1022) ||
 996              (SVR_SOC_VER(svr) == SVR_P1013))) {
 997                 fsl_sata_reg_t *reg;
 998
 999                 /* first SATA controller */
1000                 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
1001                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
1002
1003                 /* second SATA controller */
1004                 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
1005                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
1006         }
1007 #endif
1008
1009         init_used_tlb_cams();
1010
1011         return 0;
1012 }
1013
1014 void arch_preboot_os(void)
1015 {
1016         u32 msr;
1017
1018         /*
1019          * We are changing interrupt offsets and are about to boot the OS so
1020          * we need to make sure we disable all async interrupts. EE is already
1021          * disabled by the time we get called.
1022          */
1023         msr = mfmsr();
1024         msr &= ~(MSR_ME|MSR_CE);
1025         mtmsr(msr);
1026 }
1027
1028 void cpu_secondary_init_r(void)
1029 {
1030 #ifdef CONFIG_U_QE
1031         uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
1032 #elif defined CONFIG_QE
1033         uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
1034 #endif
1035
1036 #ifdef CONFIG_QE
1037         qe_init(qe_base);
1038         qe_reset();
1039 #endif
1040 }
1041
1042 #ifdef CONFIG_BOARD_LATE_INIT
1043 int board_late_init(void)
1044 {
1045 #ifdef CONFIG_CHAIN_OF_TRUST
1046         fsl_setenv_chain_of_trust();
1047 #endif
1048
1049         return 0;
1050 }
1051 #endif