8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
24 config TARGET_SOCRATES
25 bool "Support socrates"
28 config TARGET_B4420QDS
29 bool "Support B4420QDS"
34 config TARGET_B4860QDS
35 bool "Support B4860QDS"
37 select BOARD_LATE_INIT if CHAIN_OF_TRUST
41 config TARGET_BSC9131RDB
42 bool "Support BSC9131RDB"
45 select BOARD_EARLY_INIT_F
47 config TARGET_BSC9132QDS
48 bool "Support BSC9132QDS"
50 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 select BOARD_EARLY_INIT_F
54 config TARGET_C29XPCIE
55 bool "Support C29XPCIE"
57 select BOARD_LATE_INIT if CHAIN_OF_TRUST
63 bool "Support P3041DS"
66 select BOARD_LATE_INIT if CHAIN_OF_TRUST
70 bool "Support P4080DS"
73 select BOARD_LATE_INIT if CHAIN_OF_TRUST
77 bool "Support P5020DS"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
84 bool "Support P5040DS"
87 select BOARD_LATE_INIT if CHAIN_OF_TRUST
90 config TARGET_MPC8536DS
91 bool "Support MPC8536DS"
93 # Use DDR3 controller with DDR2 DIMMs on this board
94 select SYS_FSL_DDRC_GEN3
97 config TARGET_MPC8541CDS
98 bool "Support MPC8541CDS"
101 config TARGET_MPC8544DS
102 bool "Support MPC8544DS"
105 config TARGET_MPC8548CDS
106 bool "Support MPC8548CDS"
108 imply ENV_IS_IN_FLASH
110 config TARGET_MPC8555CDS
111 bool "Support MPC8555CDS"
114 config TARGET_MPC8568MDS
115 bool "Support MPC8568MDS"
118 config TARGET_MPC8569MDS
119 bool "Support MPC8569MDS"
122 config TARGET_MPC8572DS
123 bool "Support MPC8572DS"
125 # Use DDR3 controller with DDR2 DIMMs on this board
126 select SYS_FSL_DDRC_GEN3
129 config TARGET_P1010RDB_PA
130 bool "Support P1010RDB_PA"
132 select BOARD_LATE_INIT if CHAIN_OF_TRUST
138 config TARGET_P1010RDB_PB
139 bool "Support P1010RDB_PB"
141 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_P1022DS
148 bool "Support P1022DS"
154 config TARGET_P1023RDB
155 bool "Support P1023RDB"
159 config TARGET_P1020MBG
160 bool "Support P1020MBG-PC"
167 config TARGET_P1020RDB_PC
168 bool "Support P1020RDB-PC"
175 config TARGET_P1020RDB_PD
176 bool "Support P1020RDB-PD"
183 config TARGET_P1020UTM
184 bool "Support P1020UTM"
191 config TARGET_P1021RDB
192 bool "Support P1021RDB"
199 config TARGET_P1024RDB
200 bool "Support P1024RDB"
207 config TARGET_P1025RDB
208 bool "Support P1025RDB"
215 config TARGET_P2020RDB
216 bool "Support P2020RDB-PC"
224 bool "Support p1_twr"
227 config TARGET_P2041RDB
228 bool "Support P2041RDB"
230 select BOARD_LATE_INIT if CHAIN_OF_TRUST
234 config TARGET_QEMU_PPCE500
235 bool "Support qemu-ppce500"
236 select ARCH_QEMU_E500
239 config TARGET_T1024QDS
240 bool "Support T1024QDS"
242 select BOARD_LATE_INIT if CHAIN_OF_TRUST
248 config TARGET_T1023RDB
249 bool "Support T1023RDB"
251 select BOARD_LATE_INIT if CHAIN_OF_TRUST
256 config TARGET_T1024RDB
257 bool "Support T1024RDB"
259 select BOARD_LATE_INIT if CHAIN_OF_TRUST
264 config TARGET_T1040QDS
265 bool "Support T1040QDS"
267 select BOARD_LATE_INIT if CHAIN_OF_TRUST
272 config TARGET_T1040RDB
273 bool "Support T1040RDB"
275 select BOARD_LATE_INIT if CHAIN_OF_TRUST
280 config TARGET_T1040D4RDB
281 bool "Support T1040D4RDB"
283 select BOARD_LATE_INIT if CHAIN_OF_TRUST
288 config TARGET_T1042RDB
289 bool "Support T1042RDB"
291 select BOARD_LATE_INIT if CHAIN_OF_TRUST
296 config TARGET_T1042D4RDB
297 bool "Support T1042D4RDB"
299 select BOARD_LATE_INIT if CHAIN_OF_TRUST
304 config TARGET_T1042RDB_PI
305 bool "Support T1042RDB_PI"
307 select BOARD_LATE_INIT if CHAIN_OF_TRUST
312 config TARGET_T2080QDS
313 bool "Support T2080QDS"
315 select BOARD_LATE_INIT if CHAIN_OF_TRUST
320 config TARGET_T2080RDB
321 bool "Support T2080RDB"
323 select BOARD_LATE_INIT if CHAIN_OF_TRUST
328 config TARGET_T2081QDS
329 bool "Support T2081QDS"
334 config TARGET_T4160QDS
335 bool "Support T4160QDS"
337 select BOARD_LATE_INIT if CHAIN_OF_TRUST
342 config TARGET_T4160RDB
343 bool "Support T4160RDB"
348 config TARGET_T4240QDS
349 bool "Support T4240QDS"
351 select BOARD_LATE_INIT if CHAIN_OF_TRUST
356 config TARGET_T4240RDB
357 bool "Support T4240RDB"
363 config TARGET_CONTROLCENTERD
364 bool "Support controlcenterd"
367 config TARGET_KMP204X
368 bool "Support kmp204x"
374 config TARGET_XPEDITE520X
375 bool "Support xpedite520x"
378 config TARGET_XPEDITE537X
379 bool "Support xpedite537x"
381 # Use DDR3 controller with DDR2 DIMMs on this board
382 select SYS_FSL_DDRC_GEN3
384 config TARGET_XPEDITE550X
385 bool "Support xpedite550x"
388 config TARGET_UCP1020
389 bool "Support uCP1020"
393 config TARGET_CYRUS_P5020
394 bool "Support Varisys Cyrus P5020"
398 config TARGET_CYRUS_P5040
399 bool "Support Varisys Cyrus P5040"
410 select SYS_FSL_DDR_VER_47
411 select SYS_FSL_ERRATUM_A004477
412 select SYS_FSL_ERRATUM_A005871
413 select SYS_FSL_ERRATUM_A006379
414 select SYS_FSL_ERRATUM_A006384
415 select SYS_FSL_ERRATUM_A006475
416 select SYS_FSL_ERRATUM_A006593
417 select SYS_FSL_ERRATUM_A007075
418 select SYS_FSL_ERRATUM_A007186
419 select SYS_FSL_ERRATUM_A007212
420 select SYS_FSL_ERRATUM_A009942
421 select SYS_FSL_HAS_DDR3
422 select SYS_FSL_HAS_SEC
423 select SYS_FSL_QORIQ_CHASSIS2
424 select SYS_FSL_SEC_BE
425 select SYS_FSL_SEC_COMPAT_4
436 select SYS_FSL_DDR_VER_47
437 select SYS_FSL_ERRATUM_A004477
438 select SYS_FSL_ERRATUM_A005871
439 select SYS_FSL_ERRATUM_A006379
440 select SYS_FSL_ERRATUM_A006384
441 select SYS_FSL_ERRATUM_A006475
442 select SYS_FSL_ERRATUM_A006593
443 select SYS_FSL_ERRATUM_A007075
444 select SYS_FSL_ERRATUM_A007186
445 select SYS_FSL_ERRATUM_A007212
446 select SYS_FSL_ERRATUM_A007907
447 select SYS_FSL_ERRATUM_A009942
448 select SYS_FSL_HAS_DDR3
449 select SYS_FSL_HAS_SEC
450 select SYS_FSL_QORIQ_CHASSIS2
451 select SYS_FSL_SEC_BE
452 select SYS_FSL_SEC_COMPAT_4
461 select SYS_FSL_DDR_VER_44
462 select SYS_FSL_ERRATUM_A004477
463 select SYS_FSL_ERRATUM_A005125
464 select SYS_FSL_ERRATUM_ESDHC111
465 select SYS_FSL_HAS_DDR3
466 select SYS_FSL_HAS_SEC
467 select SYS_FSL_SEC_BE
468 select SYS_FSL_SEC_COMPAT_4
476 select SYS_FSL_DDR_VER_46
477 select SYS_FSL_ERRATUM_A004477
478 select SYS_FSL_ERRATUM_A005125
479 select SYS_FSL_ERRATUM_A005434
480 select SYS_FSL_ERRATUM_ESDHC111
481 select SYS_FSL_ERRATUM_I2C_A004447
482 select SYS_FSL_ERRATUM_IFC_A002769
483 select SYS_FSL_HAS_DDR3
484 select SYS_FSL_HAS_SEC
485 select SYS_FSL_SEC_BE
486 select SYS_FSL_SEC_COMPAT_4
487 select SYS_PPC_E500_USE_DEBUG_TLB
496 select SYS_FSL_DDR_VER_46
497 select SYS_FSL_ERRATUM_A005125
498 select SYS_FSL_ERRATUM_ESDHC111
499 select SYS_FSL_HAS_DDR3
500 select SYS_FSL_HAS_SEC
501 select SYS_FSL_SEC_BE
502 select SYS_FSL_SEC_COMPAT_6
503 select SYS_PPC_E500_USE_DEBUG_TLB
510 select SYS_FSL_ERRATUM_A004508
511 select SYS_FSL_ERRATUM_A005125
512 select SYS_FSL_HAS_DDR2
513 select SYS_FSL_HAS_DDR3
514 select SYS_FSL_HAS_SEC
515 select SYS_FSL_SEC_BE
516 select SYS_FSL_SEC_COMPAT_2
517 select SYS_PPC_E500_USE_DEBUG_TLB
525 select SYS_FSL_HAS_DDR1
530 select SYS_FSL_HAS_DDR1
531 select SYS_FSL_HAS_SEC
532 select SYS_FSL_SEC_BE
533 select SYS_FSL_SEC_COMPAT_2
538 select SYS_FSL_ERRATUM_A005125
539 select SYS_FSL_HAS_DDR2
540 select SYS_FSL_HAS_SEC
541 select SYS_FSL_SEC_BE
542 select SYS_FSL_SEC_COMPAT_2
543 select SYS_PPC_E500_USE_DEBUG_TLB
549 select SYS_FSL_ERRATUM_A005125
550 select SYS_FSL_ERRATUM_NMG_DDR120
551 select SYS_FSL_ERRATUM_NMG_LBC103
552 select SYS_FSL_ERRATUM_NMG_ETSEC129
553 select SYS_FSL_ERRATUM_I2C_A004447
554 select SYS_FSL_HAS_DDR2
555 select SYS_FSL_HAS_DDR1
556 select SYS_FSL_HAS_SEC
557 select SYS_FSL_SEC_BE
558 select SYS_FSL_SEC_COMPAT_2
559 select SYS_PPC_E500_USE_DEBUG_TLB
560 imply ENV_IS_IN_FLASH
565 select SYS_FSL_HAS_DDR1
566 select SYS_FSL_HAS_SEC
567 select SYS_FSL_SEC_BE
568 select SYS_FSL_SEC_COMPAT_2
573 select SYS_FSL_HAS_DDR1
578 select SYS_FSL_HAS_DDR2
579 select SYS_FSL_HAS_SEC
580 select SYS_FSL_SEC_BE
581 select SYS_FSL_SEC_COMPAT_2
586 select SYS_FSL_ERRATUM_A004508
587 select SYS_FSL_ERRATUM_A005125
588 select SYS_FSL_HAS_DDR3
589 select SYS_FSL_HAS_SEC
590 select SYS_FSL_SEC_BE
591 select SYS_FSL_SEC_COMPAT_2
598 select SYS_FSL_ERRATUM_A004508
599 select SYS_FSL_ERRATUM_A005125
600 select SYS_FSL_ERRATUM_DDR_115
601 select SYS_FSL_ERRATUM_DDR111_DDR134
602 select SYS_FSL_HAS_DDR2
603 select SYS_FSL_HAS_DDR3
604 select SYS_FSL_HAS_SEC
605 select SYS_FSL_SEC_BE
606 select SYS_FSL_SEC_COMPAT_2
607 select SYS_PPC_E500_USE_DEBUG_TLB
610 imply ENV_IS_IN_FLASH
615 select SYS_FSL_ERRATUM_A004477
616 select SYS_FSL_ERRATUM_A004508
617 select SYS_FSL_ERRATUM_A005125
618 select SYS_FSL_ERRATUM_A006261
619 select SYS_FSL_ERRATUM_A007075
620 select SYS_FSL_ERRATUM_ESDHC111
621 select SYS_FSL_ERRATUM_I2C_A004447
622 select SYS_FSL_ERRATUM_IFC_A002769
623 select SYS_FSL_ERRATUM_P1010_A003549
624 select SYS_FSL_ERRATUM_SEC_A003571
625 select SYS_FSL_ERRATUM_IFC_A003399
626 select SYS_FSL_HAS_DDR3
627 select SYS_FSL_HAS_SEC
628 select SYS_FSL_SEC_BE
629 select SYS_FSL_SEC_COMPAT_4
630 select SYS_PPC_E500_USE_DEBUG_TLB
640 select SYS_FSL_ERRATUM_A004508
641 select SYS_FSL_ERRATUM_A005125
642 select SYS_FSL_ERRATUM_ELBC_A001
643 select SYS_FSL_ERRATUM_ESDHC111
644 select SYS_FSL_HAS_DDR3
645 select SYS_FSL_HAS_SEC
646 select SYS_FSL_SEC_BE
647 select SYS_FSL_SEC_COMPAT_2
648 select SYS_PPC_E500_USE_DEBUG_TLB
654 select SYS_FSL_ERRATUM_A004508
655 select SYS_FSL_ERRATUM_A005125
656 select SYS_FSL_ERRATUM_ELBC_A001
657 select SYS_FSL_ERRATUM_ESDHC111
658 select SYS_FSL_HAS_DDR3
659 select SYS_FSL_HAS_SEC
660 select SYS_FSL_SEC_BE
661 select SYS_FSL_SEC_COMPAT_2
662 select SYS_PPC_E500_USE_DEBUG_TLB
670 select SYS_FSL_ERRATUM_A004508
671 select SYS_FSL_ERRATUM_A005125
672 select SYS_FSL_ERRATUM_ELBC_A001
673 select SYS_FSL_ERRATUM_ESDHC111
674 select SYS_FSL_HAS_DDR3
675 select SYS_FSL_HAS_SEC
676 select SYS_FSL_SEC_BE
677 select SYS_FSL_SEC_COMPAT_2
678 select SYS_PPC_E500_USE_DEBUG_TLB
686 select SYS_FSL_ERRATUM_A004477
687 select SYS_FSL_ERRATUM_A004508
688 select SYS_FSL_ERRATUM_A005125
689 select SYS_FSL_ERRATUM_ELBC_A001
690 select SYS_FSL_ERRATUM_ESDHC111
691 select SYS_FSL_ERRATUM_SATA_A001
692 select SYS_FSL_HAS_DDR3
693 select SYS_FSL_HAS_SEC
694 select SYS_FSL_SEC_BE
695 select SYS_FSL_SEC_COMPAT_2
696 select SYS_PPC_E500_USE_DEBUG_TLB
702 select SYS_FSL_ERRATUM_A004508
703 select SYS_FSL_ERRATUM_A005125
704 select SYS_FSL_ERRATUM_I2C_A004447
705 select SYS_FSL_HAS_DDR3
706 select SYS_FSL_HAS_SEC
707 select SYS_FSL_SEC_BE
708 select SYS_FSL_SEC_COMPAT_4
714 select SYS_FSL_ERRATUM_A004508
715 select SYS_FSL_ERRATUM_A005125
716 select SYS_FSL_ERRATUM_ELBC_A001
717 select SYS_FSL_ERRATUM_ESDHC111
718 select SYS_FSL_HAS_DDR3
719 select SYS_FSL_HAS_SEC
720 select SYS_FSL_SEC_BE
721 select SYS_FSL_SEC_COMPAT_2
722 select SYS_PPC_E500_USE_DEBUG_TLB
731 select SYS_FSL_ERRATUM_A004508
732 select SYS_FSL_ERRATUM_A005125
733 select SYS_FSL_ERRATUM_ELBC_A001
734 select SYS_FSL_ERRATUM_ESDHC111
735 select SYS_FSL_HAS_DDR3
736 select SYS_FSL_HAS_SEC
737 select SYS_FSL_SEC_BE
738 select SYS_FSL_SEC_COMPAT_2
739 select SYS_PPC_E500_USE_DEBUG_TLB
746 select SYS_FSL_ERRATUM_A004477
747 select SYS_FSL_ERRATUM_A004508
748 select SYS_FSL_ERRATUM_A005125
749 select SYS_FSL_ERRATUM_ESDHC111
750 select SYS_FSL_ERRATUM_ESDHC_A001
751 select SYS_FSL_HAS_DDR3
752 select SYS_FSL_HAS_SEC
753 select SYS_FSL_SEC_BE
754 select SYS_FSL_SEC_COMPAT_2
755 select SYS_PPC_E500_USE_DEBUG_TLB
764 select SYS_FSL_ERRATUM_A004510
765 select SYS_FSL_ERRATUM_A004849
766 select SYS_FSL_ERRATUM_A006261
767 select SYS_FSL_ERRATUM_CPU_A003999
768 select SYS_FSL_ERRATUM_DDR_A003
769 select SYS_FSL_ERRATUM_DDR_A003474
770 select SYS_FSL_ERRATUM_ESDHC111
771 select SYS_FSL_ERRATUM_I2C_A004447
772 select SYS_FSL_ERRATUM_NMG_CPU_A011
773 select SYS_FSL_ERRATUM_SRIO_A004034
774 select SYS_FSL_ERRATUM_USB14
775 select SYS_FSL_HAS_DDR3
776 select SYS_FSL_HAS_SEC
777 select SYS_FSL_QORIQ_CHASSIS1
778 select SYS_FSL_SEC_BE
779 select SYS_FSL_SEC_COMPAT_4
787 select SYS_FSL_DDR_VER_44
788 select SYS_FSL_ERRATUM_A004510
789 select SYS_FSL_ERRATUM_A004849
790 select SYS_FSL_ERRATUM_A005812
791 select SYS_FSL_ERRATUM_A006261
792 select SYS_FSL_ERRATUM_CPU_A003999
793 select SYS_FSL_ERRATUM_DDR_A003
794 select SYS_FSL_ERRATUM_DDR_A003474
795 select SYS_FSL_ERRATUM_ESDHC111
796 select SYS_FSL_ERRATUM_I2C_A004447
797 select SYS_FSL_ERRATUM_NMG_CPU_A011
798 select SYS_FSL_ERRATUM_SRIO_A004034
799 select SYS_FSL_ERRATUM_USB14
800 select SYS_FSL_HAS_DDR3
801 select SYS_FSL_HAS_SEC
802 select SYS_FSL_QORIQ_CHASSIS1
803 select SYS_FSL_SEC_BE
804 select SYS_FSL_SEC_COMPAT_4
813 select SYS_FSL_DDR_VER_44
814 select SYS_FSL_ERRATUM_A004510
815 select SYS_FSL_ERRATUM_A004580
816 select SYS_FSL_ERRATUM_A004849
817 select SYS_FSL_ERRATUM_A005812
818 select SYS_FSL_ERRATUM_A007075
819 select SYS_FSL_ERRATUM_CPC_A002
820 select SYS_FSL_ERRATUM_CPC_A003
821 select SYS_FSL_ERRATUM_CPU_A003999
822 select SYS_FSL_ERRATUM_DDR_A003
823 select SYS_FSL_ERRATUM_DDR_A003474
824 select SYS_FSL_ERRATUM_ELBC_A001
825 select SYS_FSL_ERRATUM_ESDHC111
826 select SYS_FSL_ERRATUM_ESDHC13
827 select SYS_FSL_ERRATUM_ESDHC135
828 select SYS_FSL_ERRATUM_I2C_A004447
829 select SYS_FSL_ERRATUM_NMG_CPU_A011
830 select SYS_FSL_ERRATUM_SRIO_A004034
831 select SYS_P4080_ERRATUM_CPU22
832 select SYS_P4080_ERRATUM_PCIE_A003
833 select SYS_P4080_ERRATUM_SERDES8
834 select SYS_P4080_ERRATUM_SERDES9
835 select SYS_P4080_ERRATUM_SERDES_A001
836 select SYS_P4080_ERRATUM_SERDES_A005
837 select SYS_FSL_HAS_DDR3
838 select SYS_FSL_HAS_SEC
839 select SYS_FSL_QORIQ_CHASSIS1
840 select SYS_FSL_SEC_BE
841 select SYS_FSL_SEC_COMPAT_4
849 select SYS_FSL_DDR_VER_44
850 select SYS_FSL_ERRATUM_A004510
851 select SYS_FSL_ERRATUM_A006261
852 select SYS_FSL_ERRATUM_DDR_A003
853 select SYS_FSL_ERRATUM_DDR_A003474
854 select SYS_FSL_ERRATUM_ESDHC111
855 select SYS_FSL_ERRATUM_I2C_A004447
856 select SYS_FSL_ERRATUM_SRIO_A004034
857 select SYS_FSL_ERRATUM_USB14
858 select SYS_FSL_HAS_DDR3
859 select SYS_FSL_HAS_SEC
860 select SYS_FSL_QORIQ_CHASSIS1
861 select SYS_FSL_SEC_BE
862 select SYS_FSL_SEC_COMPAT_4
871 select SYS_FSL_DDR_VER_44
872 select SYS_FSL_ERRATUM_A004510
873 select SYS_FSL_ERRATUM_A004699
874 select SYS_FSL_ERRATUM_A005812
875 select SYS_FSL_ERRATUM_A006261
876 select SYS_FSL_ERRATUM_DDR_A003
877 select SYS_FSL_ERRATUM_DDR_A003474
878 select SYS_FSL_ERRATUM_ESDHC111
879 select SYS_FSL_ERRATUM_USB14
880 select SYS_FSL_HAS_DDR3
881 select SYS_FSL_HAS_SEC
882 select SYS_FSL_QORIQ_CHASSIS1
883 select SYS_FSL_SEC_BE
884 select SYS_FSL_SEC_COMPAT_4
889 config ARCH_QEMU_E500
896 select SYS_FSL_DDR_VER_50
897 select SYS_FSL_ERRATUM_A008378
898 select SYS_FSL_ERRATUM_A009663
899 select SYS_FSL_ERRATUM_A009942
900 select SYS_FSL_ERRATUM_ESDHC111
901 select SYS_FSL_HAS_DDR3
902 select SYS_FSL_HAS_DDR4
903 select SYS_FSL_HAS_SEC
904 select SYS_FSL_QORIQ_CHASSIS2
905 select SYS_FSL_SEC_BE
906 select SYS_FSL_SEC_COMPAT_5
915 select SYS_FSL_DDR_VER_50
916 select SYS_FSL_ERRATUM_A008378
917 select SYS_FSL_ERRATUM_A009663
918 select SYS_FSL_ERRATUM_A009942
919 select SYS_FSL_ERRATUM_ESDHC111
920 select SYS_FSL_HAS_DDR3
921 select SYS_FSL_HAS_DDR4
922 select SYS_FSL_HAS_SEC
923 select SYS_FSL_QORIQ_CHASSIS2
924 select SYS_FSL_SEC_BE
925 select SYS_FSL_SEC_COMPAT_5
935 select SYS_FSL_DDR_VER_50
936 select SYS_FSL_ERRATUM_A008044
937 select SYS_FSL_ERRATUM_A008378
938 select SYS_FSL_ERRATUM_A009663
939 select SYS_FSL_ERRATUM_A009942
940 select SYS_FSL_ERRATUM_ESDHC111
941 select SYS_FSL_HAS_DDR3
942 select SYS_FSL_HAS_DDR4
943 select SYS_FSL_HAS_SEC
944 select SYS_FSL_QORIQ_CHASSIS2
945 select SYS_FSL_SEC_BE
946 select SYS_FSL_SEC_COMPAT_5
956 select SYS_FSL_DDR_VER_50
957 select SYS_FSL_ERRATUM_A008044
958 select SYS_FSL_ERRATUM_A008378
959 select SYS_FSL_ERRATUM_A009663
960 select SYS_FSL_ERRATUM_A009942
961 select SYS_FSL_ERRATUM_ESDHC111
962 select SYS_FSL_HAS_DDR3
963 select SYS_FSL_HAS_DDR4
964 select SYS_FSL_HAS_SEC
965 select SYS_FSL_QORIQ_CHASSIS2
966 select SYS_FSL_SEC_BE
967 select SYS_FSL_SEC_COMPAT_5
978 select SYS_FSL_DDR_VER_47
979 select SYS_FSL_ERRATUM_A006379
980 select SYS_FSL_ERRATUM_A006593
981 select SYS_FSL_ERRATUM_A007186
982 select SYS_FSL_ERRATUM_A007212
983 select SYS_FSL_ERRATUM_A007815
984 select SYS_FSL_ERRATUM_A007907
985 select SYS_FSL_ERRATUM_A009942
986 select SYS_FSL_ERRATUM_ESDHC111
987 select SYS_FSL_HAS_DDR3
988 select SYS_FSL_HAS_SEC
989 select SYS_FSL_QORIQ_CHASSIS2
990 select SYS_FSL_SEC_BE
991 select SYS_FSL_SEC_COMPAT_4
1002 select SYS_FSL_DDR_VER_47
1003 select SYS_FSL_ERRATUM_A006379
1004 select SYS_FSL_ERRATUM_A006593
1005 select SYS_FSL_ERRATUM_A007186
1006 select SYS_FSL_ERRATUM_A007212
1007 select SYS_FSL_ERRATUM_A009942
1008 select SYS_FSL_ERRATUM_ESDHC111
1009 select SYS_FSL_HAS_DDR3
1010 select SYS_FSL_HAS_SEC
1011 select SYS_FSL_QORIQ_CHASSIS2
1012 select SYS_FSL_SEC_BE
1013 select SYS_FSL_SEC_COMPAT_4
1023 select SYS_FSL_DDR_VER_47
1024 select SYS_FSL_ERRATUM_A004468
1025 select SYS_FSL_ERRATUM_A005871
1026 select SYS_FSL_ERRATUM_A006379
1027 select SYS_FSL_ERRATUM_A006593
1028 select SYS_FSL_ERRATUM_A007186
1029 select SYS_FSL_ERRATUM_A007798
1030 select SYS_FSL_ERRATUM_A009942
1031 select SYS_FSL_HAS_DDR3
1032 select SYS_FSL_HAS_SEC
1033 select SYS_FSL_QORIQ_CHASSIS2
1034 select SYS_FSL_SEC_BE
1035 select SYS_FSL_SEC_COMPAT_4
1046 select SYS_FSL_DDR_VER_47
1047 select SYS_FSL_ERRATUM_A004468
1048 select SYS_FSL_ERRATUM_A005871
1049 select SYS_FSL_ERRATUM_A006261
1050 select SYS_FSL_ERRATUM_A006379
1051 select SYS_FSL_ERRATUM_A006593
1052 select SYS_FSL_ERRATUM_A007186
1053 select SYS_FSL_ERRATUM_A007798
1054 select SYS_FSL_ERRATUM_A007815
1055 select SYS_FSL_ERRATUM_A007907
1056 select SYS_FSL_ERRATUM_A009942
1057 select SYS_FSL_HAS_DDR3
1058 select SYS_FSL_HAS_SEC
1059 select SYS_FSL_QORIQ_CHASSIS2
1060 select SYS_FSL_SEC_BE
1061 select SYS_FSL_SEC_COMPAT_4
1075 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1080 Enble PowerPC E500MC core
1085 Enable PowerPC E6500 core
1090 Use Freescale common code for Local Access Window
1095 Enable Freescale Secure Boot feature. Normally selected
1096 by defconfig. If unsure, do not change.
1099 int "Maximum number of CPUs permitted for MPC85xx"
1100 default 12 if ARCH_T4240
1101 default 8 if ARCH_P4080 || \
1103 default 4 if ARCH_B4860 || \
1111 default 2 if ARCH_B4420 || \
1126 Set this number to the maximum number of possible CPUs in the SoC.
1127 SoCs may have multiple clusters with each cluster may have multiple
1128 ports. If some ports are reserved but higher ports are used for
1129 cores, count the reserved ports. This will allocate enough memory
1130 in spin table to properly handle all cores.
1132 config SYS_CCSRBAR_DEFAULT
1133 hex "Default CCSRBAR address"
1134 default 0xff700000 if ARCH_BSC9131 || \
1155 default 0xff600000 if ARCH_P1023
1156 default 0xfe000000 if ARCH_B4420 || \
1171 default 0xe0000000 if ARCH_QEMU_E500
1173 Default value of CCSRBAR comes from power-on-reset. It
1174 is fixed on each SoC. Some SoCs can have different value
1175 if changed by pre-boot regime. The value here must match
1176 the current value in SoC. If not sure, do not change.
1178 config SYS_FSL_ERRATUM_A004468
1181 config SYS_FSL_ERRATUM_A004477
1184 config SYS_FSL_ERRATUM_A004508
1187 config SYS_FSL_ERRATUM_A004580
1190 config SYS_FSL_ERRATUM_A004699
1193 config SYS_FSL_ERRATUM_A004849
1196 config SYS_FSL_ERRATUM_A004510
1199 config SYS_FSL_ERRATUM_A004510_SVR_REV
1201 depends on SYS_FSL_ERRATUM_A004510
1202 default 0x20 if ARCH_P4080
1205 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1207 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1210 config SYS_FSL_ERRATUM_A005125
1213 config SYS_FSL_ERRATUM_A005434
1216 config SYS_FSL_ERRATUM_A005812
1219 config SYS_FSL_ERRATUM_A005871
1222 config SYS_FSL_ERRATUM_A006261
1225 config SYS_FSL_ERRATUM_A006379
1228 config SYS_FSL_ERRATUM_A006384
1231 config SYS_FSL_ERRATUM_A006475
1234 config SYS_FSL_ERRATUM_A006593
1237 config SYS_FSL_ERRATUM_A007075
1240 config SYS_FSL_ERRATUM_A007186
1243 config SYS_FSL_ERRATUM_A007212
1246 config SYS_FSL_ERRATUM_A007815
1249 config SYS_FSL_ERRATUM_A007798
1252 config SYS_FSL_ERRATUM_A007907
1255 config SYS_FSL_ERRATUM_A008044
1258 config SYS_FSL_ERRATUM_CPC_A002
1261 config SYS_FSL_ERRATUM_CPC_A003
1264 config SYS_FSL_ERRATUM_CPU_A003999
1267 config SYS_FSL_ERRATUM_ELBC_A001
1270 config SYS_FSL_ERRATUM_I2C_A004447
1273 config SYS_FSL_A004447_SVR_REV
1275 depends on SYS_FSL_ERRATUM_I2C_A004447
1276 default 0x00 if ARCH_MPC8548
1277 default 0x10 if ARCH_P1010
1278 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1279 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1281 config SYS_FSL_ERRATUM_IFC_A002769
1284 config SYS_FSL_ERRATUM_IFC_A003399
1287 config SYS_FSL_ERRATUM_NMG_CPU_A011
1290 config SYS_FSL_ERRATUM_NMG_ETSEC129
1293 config SYS_FSL_ERRATUM_NMG_LBC103
1296 config SYS_FSL_ERRATUM_P1010_A003549
1299 config SYS_FSL_ERRATUM_SATA_A001
1302 config SYS_FSL_ERRATUM_SEC_A003571
1305 config SYS_FSL_ERRATUM_SRIO_A004034
1308 config SYS_FSL_ERRATUM_USB14
1311 config SYS_P4080_ERRATUM_CPU22
1314 config SYS_P4080_ERRATUM_PCIE_A003
1317 config SYS_P4080_ERRATUM_SERDES8
1320 config SYS_P4080_ERRATUM_SERDES9
1323 config SYS_P4080_ERRATUM_SERDES_A001
1326 config SYS_P4080_ERRATUM_SERDES_A005
1329 config SYS_FSL_QORIQ_CHASSIS1
1332 config SYS_FSL_QORIQ_CHASSIS2
1335 config SYS_FSL_NUM_LAWS
1336 int "Number of local access windows"
1338 default 32 if ARCH_B4420 || \
1349 default 16 if ARCH_T1023 || \
1353 default 12 if ARCH_BSC9131 || \
1367 default 10 if ARCH_MPC8544 || \
1371 default 8 if ARCH_MPC8540 || \
1376 Number of local access windows. This is fixed per SoC.
1377 If not sure, do not change.
1379 config SYS_FSL_THREADS_PER_CORE
1384 config SYS_NUM_TLBCAMS
1385 int "Number of TLB CAM entries"
1386 default 64 if E500MC
1389 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1390 16 for other E500 SoCs.
1395 config SYS_PPC_E500_USE_DEBUG_TLB
1404 config SYS_PPC_E500_DEBUG_TLB
1405 int "Temporary TLB entry for external debugger"
1406 depends on SYS_PPC_E500_USE_DEBUG_TLB
1407 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1408 default 1 if ARCH_MPC8536
1409 default 2 if ARCH_MPC8572 || \
1417 default 3 if ARCH_P1010 || \
1421 Select a temporary TLB entry to be used during boot to work
1422 around limitations in e500v1 and e500v2 external debugger
1423 support. This reduces the portions of the boot code where
1424 breakpoints and single stepping do not work. The value of this
1425 symbol should be set to the TLB1 entry to be used for this
1426 purpose. If unsure, do not change.
1428 config SYS_FSL_IFC_CLK_DIV
1429 int "Divider of platform clock"
1431 default 2 if ARCH_B4420 || \
1441 Defines divider of platform clock(clock input to
1444 config SYS_FSL_LBC_CLK_DIV
1445 int "Divider of platform clock"
1446 depends on FSL_ELBC || ARCH_MPC8540 || \
1447 ARCH_MPC8548 || ARCH_MPC8541 || \
1448 ARCH_MPC8555 || ARCH_MPC8560 || \
1451 default 2 if ARCH_P2041 || \
1459 Defines divider of platform clock(clock input to
1462 source "board/freescale/b4860qds/Kconfig"
1463 source "board/freescale/bsc9131rdb/Kconfig"
1464 source "board/freescale/bsc9132qds/Kconfig"
1465 source "board/freescale/c29xpcie/Kconfig"
1466 source "board/freescale/corenet_ds/Kconfig"
1467 source "board/freescale/mpc8536ds/Kconfig"
1468 source "board/freescale/mpc8541cds/Kconfig"
1469 source "board/freescale/mpc8544ds/Kconfig"
1470 source "board/freescale/mpc8548cds/Kconfig"
1471 source "board/freescale/mpc8555cds/Kconfig"
1472 source "board/freescale/mpc8568mds/Kconfig"
1473 source "board/freescale/mpc8569mds/Kconfig"
1474 source "board/freescale/mpc8572ds/Kconfig"
1475 source "board/freescale/p1010rdb/Kconfig"
1476 source "board/freescale/p1022ds/Kconfig"
1477 source "board/freescale/p1023rdb/Kconfig"
1478 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1479 source "board/freescale/p1_twr/Kconfig"
1480 source "board/freescale/p2041rdb/Kconfig"
1481 source "board/freescale/qemu-ppce500/Kconfig"
1482 source "board/freescale/t102xqds/Kconfig"
1483 source "board/freescale/t102xrdb/Kconfig"
1484 source "board/freescale/t1040qds/Kconfig"
1485 source "board/freescale/t104xrdb/Kconfig"
1486 source "board/freescale/t208xqds/Kconfig"
1487 source "board/freescale/t208xrdb/Kconfig"
1488 source "board/freescale/t4qds/Kconfig"
1489 source "board/freescale/t4rdb/Kconfig"
1490 source "board/gdsys/p1022/Kconfig"
1491 source "board/keymile/kmp204x/Kconfig"
1492 source "board/sbc8548/Kconfig"
1493 source "board/socrates/Kconfig"
1494 source "board/varisys/cyrus/Kconfig"
1495 source "board/xes/xpedite520x/Kconfig"
1496 source "board/xes/xpedite537x/Kconfig"
1497 source "board/xes/xpedite550x/Kconfig"
1498 source "board/Arcturus/ucp1020/Kconfig"