1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Freescale Semiconductor, Inc. 2007
5 * Author: Scott Wood <scottwood@freescale.com>,
6 * with some bits from older board-specific PCI initialization.
12 #include <linux/delay.h>
14 #if defined(CONFIG_OF_LIBFDT)
15 #include <linux/libfdt.h>
16 #include <fdt_support.h>
19 #include <asm/mpc8349_pci.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 static struct pci_controller pci_hose[MAX_BUSES];
26 static int pci_num_buses;
28 static void pci_init_bus(int bus, struct pci_region *reg)
30 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
31 volatile pot83xx_t *pot = immr->ios.pot;
32 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
33 struct pci_controller *hose = &pci_hose[bus];
41 /* Setup outbound translation windows */
42 for (i = 0; i < 3; i++, reg++, pot++) {
46 hose->regions[i] = *reg;
49 pot->potar = reg->bus_start >> 12;
50 pot->pobar = reg->phys_start >> 12;
51 pot->pocmr = ~(reg->size - 1) >> 12;
53 if (reg->flags & PCI_REGION_IO)
54 pot->pocmr |= POCMR_IO;
55 #ifdef CONFIG_83XX_PCI_STREAMING
56 else if (reg->flags & PCI_REGION_PREFETCH)
57 pot->pocmr |= POCMR_SE;
61 pot->pocmr |= POCMR_DST;
63 pot->pocmr |= POCMR_EN;
66 /* Point inbound translation at RAM */
69 pci_ctrl->piebar1 = 0;
70 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
71 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
73 i = hose->region_count++;
74 hose->regions[i].bus_start = 0;
75 hose->regions[i].phys_start = 0;
76 hose->regions[i].size = gd->ram_size;
77 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
79 hose->first_busno = pci_last_busno() + 1;
80 hose->last_busno = 0xff;
82 pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
83 CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
85 pci_register_hose(hose);
88 * Write to Command register
91 dev = PCI_BDF(hose->first_busno, 0, 0);
92 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
93 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
94 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
97 * Clear non-reserved bits in status register.
99 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
100 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
101 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
103 #ifdef CONFIG_PCI_SCAN_SHOW
104 printf("PCI: Bus Dev VenId DevId Class Int\n");
106 #ifndef CONFIG_PCISLAVE
110 hose->last_busno = pci_hose_scan(hose);
115 * The caller must have already set OCCR, and the PCI_LAW BARs
116 * must have been set to cover all of the requested regions.
118 * If fewer than three regions are requested, then the region
119 * list is terminated with a region of size 0.
121 void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
123 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
126 if (num_buses > MAX_BUSES) {
127 printf("%d PCI buses requested, %d supported\n",
128 num_buses, MAX_BUSES);
130 num_buses = MAX_BUSES;
133 pci_num_buses = num_buses;
136 * Release PCI RST Output signal.
137 * Power on to RST high must be at least 100 ms as per PCI spec.
138 * On warm boots only 1 ms is required, but we play it safe.
142 for (i = 0; i < num_buses; i++)
143 immr->pci_ctrl[i].gcr = 1;
146 * RST high to first config access must be at least 2^25 cycles
147 * as per PCI spec. This could be cut in half if we know we're
148 * running at 66MHz. This could be insufficiently long if we're
149 * running the PCI bus at significantly less than 33MHz.
153 for (i = 0; i < num_buses; i++)
154 pci_init_bus(i, reg[i]);
157 #ifdef CONFIG_PCISLAVE
159 #define PCI_FUNCTION_CONFIG 0x44
160 #define PCI_FUNCTION_CFG_LOCK 0x20
163 * Unlock the configuration bit so that the host system can begin booting
165 * This should be used after you have:
166 * 1) Called mpc83xx_pci_init()
167 * 2) Set up your inbound translation windows to the appropriate size
169 void mpc83xx_pcislave_unlock(int bus)
171 struct pci_controller *hose = &pci_hose[bus];
175 /* Unlock configuration lock in PCI function configuration register */
176 dev = PCI_BDF(hose->first_busno, 0, 0);
177 pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16);
178 reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
179 pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
181 /* The configuration bit is now unlocked, so we can scan the bus */
182 hose->last_busno = pci_hose_scan(hose);
186 #if defined(CONFIG_OF_LIBFDT)
187 void ft_pci_setup(void *blob, bd_t *bd)
193 if (pci_num_buses < 1)
196 nodeoffset = fdt_path_offset(blob, "/aliases");
197 if (nodeoffset >= 0) {
198 path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
200 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
201 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
202 do_fixup_by_path(blob, path, "bus-range",
203 &tmp, sizeof(tmp), 1);
205 tmp[0] = cpu_to_be32(gd->pci_clk);
206 do_fixup_by_path(blob, path, "clock-frequency",
207 &tmp, sizeof(tmp[0]), 1);
210 if (pci_num_buses < 2)
213 path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
215 tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
216 tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
217 do_fixup_by_path(blob, path, "bus-range",
218 &tmp, sizeof(tmp), 1);
220 tmp[0] = cpu_to_be32(gd->pci_clk);
221 do_fixup_by_path(blob, path, "clock-frequency",
222 &tmp, sizeof(tmp[0]), 1);
226 #endif /* CONFIG_OF_LIBFDT */