arch/powerpc/cpu/mpc83xx/cpu_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm-offsets.h>
   8 #include <mpc83xx.h>
   9 #include <ioports.h>
  10 #include <asm/io.h>
  11 #include <asm/processor.h>
  12 #ifdef CONFIG_USB_EHCI_FSL
  13 #include <usb/ehci-ci.h>
  14 #endif
  15 #include <linux/delay.h>
  16
  17 #include "lblaw/lblaw.h"
  18 #include "elbc/elbc.h"
  19 #include "sysio/sysio.h"
  20 #include "arbiter/arbiter.h"
  21 #include "initreg/initreg.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #ifdef CONFIG_QE
  26 extern qe_iop_conf_t qe_iop_conf_tab[];
  27 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  28                          int open_drain, int assign);
  29 extern void qe_init(uint qe_base);
  30 extern void qe_reset(void);
  31
  32 static void config_qe_ioports(void)
  33 {
  34         u8      port, pin;
  35         int     dir, open_drain, assign;
  36         int     i;
  37
  38         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  39                 port            = qe_iop_conf_tab[i].port;
  40                 pin             = qe_iop_conf_tab[i].pin;
  41                 dir             = qe_iop_conf_tab[i].dir;
  42                 open_drain      = qe_iop_conf_tab[i].open_drain;
  43                 assign          = qe_iop_conf_tab[i].assign;
  44                 qe_config_iopin(port, pin, dir, open_drain, assign);
  45         }
  46 }
  47 #endif
  48
  49 /*
  50  * Breathe some life into the CPU...
  51  *
  52  * Set up the memory map,
  53  * initialize a bunch of registers,
  54  * initialize the UPM's
  55  */
  56 void cpu_init_f (volatile immap_t * im)
  57 {
  58         __be32 sccr_mask =
  59 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  60                 SCCR_ENCCM |
  61 #endif
  62 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  63                 SCCR_PCICM |
  64 #endif
  65 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
  66                 SCCR_PCIEXP1CM |
  67 #endif
  68 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
  69                 SCCR_PCIEXP2CM |
  70 #endif
  71 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  72                 SCCR_TSECCM |
  73 #endif
  74 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  75                 SCCR_TSEC1CM |
  76 #endif
  77 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  78                 SCCR_TSEC2CM |
  79 #endif
  80 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  81                 SCCR_TSEC1ON |
  82 #endif
  83 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  84                 SCCR_TSEC2ON |
  85 #endif
  86 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  87                 SCCR_USBMPHCM |
  88 #endif
  89 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  90                 SCCR_USBDRCM |
  91 #endif
  92 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  93                 SCCR_SATACM |
  94 #endif
  95                 0;
  96         __be32 sccr_val =
  97 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  98                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
  99 #endif
 100 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 101                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 102 #endif
 103 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
 104                 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
 105 #endif
 106 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
 107                 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
 108 #endif
 109 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 110                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 111 #endif
 112 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 113                 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 114 #endif
 115 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 116                 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 117 #endif
 118 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 119                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 120 #endif
 121 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 122                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 123 #endif
 124 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 125                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 126 #endif
 127 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 128                 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 129 #endif
 130 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 131                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 132 #endif
 133                 0;
 134
 135         /* Pointer is writable since we allocated a register for it */
 136         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 137
 138         /* global data region was cleared in start.S */
 139
 140         /* system performance tweaking */
 141         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 142
 143         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 144
 145         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 146
 147         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 148         gd->arch.reset_status = __raw_readl(&im->reset.rsr);
 149         __raw_writel(~(RSR_RES), &im->reset.rsr);
 150
 151         /* AER - Arbiter Event Register - store status */
 152         gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 153         gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 154
 155         /*
 156          * RMR - Reset Mode Register
 157          * contains checkstop reset enable (4.6.1.4)
 158          */
 159         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 160
 161         /* LCRR - Clock Ratio Register (10.3.1.16)
 162          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 163          */
 164         clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
 165         __raw_readl(&im->im_lbc.lcrr);
 166         isync();
 167
 168         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 169         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 170
 171         /* System General Purpose Register */
 172 #ifdef CONFIG_SYS_SICRH
 173 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
 174         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 175         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 176                      &im->sysconf.sicrh);
 177 #else
 178         __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 179 #endif
 180 #endif
 181 #ifdef CONFIG_SYS_SICRL
 182         __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 183 #endif
 184 #ifdef CONFIG_SYS_GPR1
 185         __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
 186 #endif
 187 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 188         __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 189 #endif
 190 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
 191         __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 192 #endif
 193
 194 #ifdef CONFIG_QE
 195         /* Config QE ioports */
 196         config_qe_ioports();
 197 #endif
 198         /* Set up preliminary BR/OR regs */
 199         init_early_memctl_regs();
 200
 201         /* Local Access window setup */
 202 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 203         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 204         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 205 #else
 206 #error  CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 207 #endif
 208
 209 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 210         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 211         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 212 #endif
 213 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 214         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 215         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 216 #endif
 217 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 218         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 219         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 220 #endif
 221 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 222         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 223         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 224 #endif
 225 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 226         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 227         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 228 #endif
 229 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 230         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 231         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 232 #endif
 233 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 234         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 235         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 236 #endif
 237 #ifdef CONFIG_SYS_GPIO1_PRELIM
 238         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 239         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 240 #endif
 241 #ifdef CONFIG_SYS_GPIO2_PRELIM
 242         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 243         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 244 #endif
 245 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
 246         uint32_t temp;
 247         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 248
 249         /* Configure interface. */
 250         setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 251
 252         /* Wait for clock to stabilize */
 253         do {
 254                 temp = __raw_readl(&ehci->control);
 255                 udelay(1000);
 256         } while (!(temp & PHY_CLK_VALID));
 257 #endif
 258 }
 259
 260 int cpu_init_r (void)
 261 {
 262 #ifdef CONFIG_QE
 263         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 264
 265         qe_init(qe_base);
 266         qe_reset();
 267 #endif
 268         return 0;
 269 }
 270
 271 /*
 272  * Print out the bus arbiter event
 273  */
 274 #if defined(CONFIG_DISPLAY_AER_FULL)
 275 static int print_83xx_arb_event(int force)
 276 {
 277         static char* event[] = {
 278                 "Address Time Out",
 279                 "Data Time Out",
 280                 "Address Only Transfer Type",
 281                 "External Control Word Transfer Type",
 282                 "Reserved Transfer Type",
 283                 "Transfer Error",
 284                 "reserved",
 285                 "reserved"
 286         };
 287         static char* master[] = {
 288                 "e300 Core Data Transaction",
 289                 "reserved",
 290                 "e300 Core Instruction Fetch",
 291                 "reserved",
 292                 "TSEC1",
 293                 "TSEC2",
 294                 "USB MPH",
 295                 "USB DR",
 296                 "Encryption Core",
 297                 "I2C Boot Sequencer",
 298                 "JTAG",
 299                 "reserved",
 300                 "eSDHC",
 301                 "PCI1",
 302                 "PCI2",
 303                 "DMA",
 304                 "QUICC Engine 00",
 305                 "QUICC Engine 01",
 306                 "QUICC Engine 10",
 307                 "QUICC Engine 11",
 308                 "reserved",
 309                 "reserved",
 310                 "reserved",
 311                 "reserved",
 312                 "SATA1",
 313                 "SATA2",
 314                 "SATA3",
 315                 "SATA4",
 316                 "reserved",
 317                 "PCI Express 1",
 318                 "PCI Express 2",
 319                 "TDM-DMAC"
 320         };
 321         static char *transfer[] = {
 322                 "Address-only, Clean Block",
 323                 "Address-only, lwarx reservation set",
 324                 "Single-beat or Burst write",
 325                 "reserved",
 326                 "Address-only, Flush Block",
 327                 "reserved",
 328                 "Burst write",
 329                 "reserved",
 330                 "Address-only, sync",
 331                 "Address-only, tlbsync",
 332                 "Single-beat or Burst read",
 333                 "Single-beat or Burst read",
 334                 "Address-only, Kill Block",
 335                 "Address-only, icbi",
 336                 "Burst read",
 337                 "reserved",
 338                 "Address-only, eieio",
 339                 "reserved",
 340                 "Single-beat write",
 341                 "reserved",
 342                 "ecowx - Illegal single-beat write",
 343                 "reserved",
 344                 "reserved",
 345                 "reserved",
 346                 "Address-only, TLB Invalidate",
 347                 "reserved",
 348                 "Single-beat or Burst read",
 349                 "reserved",
 350                 "eciwx - Illegal single-beat read",
 351                 "reserved",
 352                 "Burst read",
 353                 "reserved"
 354         };
 355
 356         int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
 357                     >> AEATR_EVENT_SHIFT;
 358         int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
 359                       >> AEATR_MSTR_ID_SHIFT;
 360         int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
 361                    >> AEATR_TBST_SHIFT;
 362         int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
 363                     >> AEATR_TSIZE_SHIFT;
 364         int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
 365                     >> AEATR_TTYPE_SHIFT;
 366
 367         if (!force && !gd->arch.arbiter_event_address)
 368                 return 0;
 369
 370         puts("Arbiter Event Status:\n");
 371         printf("       Event Address: 0x%08lX\n",
 372                gd->arch.arbiter_event_address);
 373         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 374         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 375         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 376                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 377         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 378
 379         return gd->arch.arbiter_event_address;
 380 }
 381
 382 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 383
 384 static int print_83xx_arb_event(int force)
 385 {
 386         if (!force && !gd->arch.arbiter_event_address)
 387                 return 0;
 388
 389         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 390                 gd->arch.arbiter_event_attributes,
 391                 gd->arch.arbiter_event_address);
 392
 393         return gd->arch.arbiter_event_address;
 394 }
 395 #endif /* CONFIG_DISPLAY_AER_xxxx */
 396
 397 #ifndef CONFIG_CPU_MPC83XX
 398 /*
 399  * Figure out the cause of the reset
 400  */
 401 int prt_83xx_rsr(void)
 402 {
 403         static struct {
 404                 ulong mask;
 405                 char *desc;
 406         } bits[] = {
 407                 {
 408                 RSR_SWSR, "Software Soft"}, {
 409                 RSR_SWHR, "Software Hard"}, {
 410                 RSR_JSRS, "JTAG Soft"}, {
 411                 RSR_CSHR, "Check Stop"}, {
 412                 RSR_SWRS, "Software Watchdog"}, {
 413                 RSR_BMRS, "Bus Monitor"}, {
 414                 RSR_SRS,  "External/Internal Soft"}, {
 415                 RSR_HRS,  "External/Internal Hard"}
 416         };
 417         static int n = ARRAY_SIZE(bits);
 418         ulong rsr = gd->arch.reset_status;
 419         int i;
 420         char *sep;
 421
 422         puts("Reset Status:");
 423
 424         sep = " ";
 425         for (i = 0; i < n; i++)
 426                 if (rsr & bits[i].mask) {
 427                         printf("%s%s", sep, bits[i].desc);
 428                         sep = ", ";
 429                 }
 430         puts("\n");
 431
 432 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 433         print_83xx_arb_event(rsr & RSR_BMRS);
 434 #endif
 435         puts("\n");
 436
 437         return 0;
 438 }
 439 #endif