arch/powerpc/cpu/mpc83xx/cpu_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm-offsets.h>
   8 #include <mpc83xx.h>
   9 #include <ioports.h>
  10 #include <asm/io.h>
  11 #include <asm/processor.h>
  12 #ifdef CONFIG_USB_EHCI_FSL
  13 #include <usb/ehci-ci.h>
  14 #endif
  15
  16 #include "lblaw/lblaw.h"
  17 #include "elbc/elbc.h"
  18 #include "sysio/sysio.h"
  19 #include "arbiter/arbiter.h"
  20 #include "initreg/initreg.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #ifdef CONFIG_QE
  25 extern qe_iop_conf_t qe_iop_conf_tab[];
  26 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  27                          int open_drain, int assign);
  28 extern void qe_init(uint qe_base);
  29 extern void qe_reset(void);
  30
  31 static void config_qe_ioports(void)
  32 {
  33         u8      port, pin;
  34         int     dir, open_drain, assign;
  35         int     i;
  36
  37         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  38                 port            = qe_iop_conf_tab[i].port;
  39                 pin             = qe_iop_conf_tab[i].pin;
  40                 dir             = qe_iop_conf_tab[i].dir;
  41                 open_drain      = qe_iop_conf_tab[i].open_drain;
  42                 assign          = qe_iop_conf_tab[i].assign;
  43                 qe_config_iopin(port, pin, dir, open_drain, assign);
  44         }
  45 }
  46 #endif
  47
  48 /*
  49  * Breathe some life into the CPU...
  50  *
  51  * Set up the memory map,
  52  * initialize a bunch of registers,
  53  * initialize the UPM's
  54  */
  55 void cpu_init_f (volatile immap_t * im)
  56 {
  57         __be32 sccr_mask =
  58 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  59                 SCCR_ENCCM |
  60 #endif
  61 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  62                 SCCR_PCICM |
  63 #endif
  64 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
  65                 SCCR_PCIEXP1CM |
  66 #endif
  67 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
  68                 SCCR_PCIEXP2CM |
  69 #endif
  70 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  71                 SCCR_TSECCM |
  72 #endif
  73 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  74                 SCCR_TSEC1CM |
  75 #endif
  76 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  77                 SCCR_TSEC2CM |
  78 #endif
  79 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  80                 SCCR_TSEC1ON |
  81 #endif
  82 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  83                 SCCR_TSEC2ON |
  84 #endif
  85 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  86                 SCCR_USBMPHCM |
  87 #endif
  88 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  89                 SCCR_USBDRCM |
  90 #endif
  91 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  92                 SCCR_SATACM |
  93 #endif
  94                 0;
  95         __be32 sccr_val =
  96 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  97                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
  98 #endif
  99 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 100                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 101 #endif
 102 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
 103                 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
 104 #endif
 105 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
 106                 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
 107 #endif
 108 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 109                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 110 #endif
 111 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 112                 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 113 #endif
 114 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 115                 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 116 #endif
 117 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 118                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 119 #endif
 120 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 121                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 122 #endif
 123 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 124                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 125 #endif
 126 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 127                 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 128 #endif
 129 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 130                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 131 #endif
 132                 0;
 133
 134         /* Pointer is writable since we allocated a register for it */
 135         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 136
 137         /* global data region was cleared in start.S */
 138
 139         /* system performance tweaking */
 140         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 141
 142         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 143
 144         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 145
 146         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 147         gd->arch.reset_status = __raw_readl(&im->reset.rsr);
 148         __raw_writel(~(RSR_RES), &im->reset.rsr);
 149
 150         /* AER - Arbiter Event Register - store status */
 151         gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 152         gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 153
 154         /*
 155          * RMR - Reset Mode Register
 156          * contains checkstop reset enable (4.6.1.4)
 157          */
 158         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 159
 160         /* LCRR - Clock Ratio Register (10.3.1.16)
 161          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 162          */
 163         clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
 164         __raw_readl(&im->im_lbc.lcrr);
 165         isync();
 166
 167         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 168         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 169
 170         /* System General Purpose Register */
 171 #ifdef CONFIG_SYS_SICRH
 172 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
 173         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 174         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 175                      &im->sysconf.sicrh);
 176 #else
 177         __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 178 #endif
 179 #endif
 180 #ifdef CONFIG_SYS_SICRL
 181         __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 182 #endif
 183 #ifdef CONFIG_SYS_GPR1
 184         __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
 185 #endif
 186 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 187         __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 188 #endif
 189 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
 190         __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 191 #endif
 192
 193 #ifdef CONFIG_QE
 194         /* Config QE ioports */
 195         config_qe_ioports();
 196 #endif
 197         /* Set up preliminary BR/OR regs */
 198         init_early_memctl_regs();
 199
 200         /* Local Access window setup */
 201 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 202         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 203         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 204 #else
 205 #error  CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 206 #endif
 207
 208 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 209         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 210         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 211 #endif
 212 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 213         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 214         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 215 #endif
 216 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 217         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 218         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 219 #endif
 220 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 221         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 222         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 223 #endif
 224 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 225         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 226         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 227 #endif
 228 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 229         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 230         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 231 #endif
 232 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 233         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 234         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 235 #endif
 236 #ifdef CONFIG_SYS_GPIO1_PRELIM
 237         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 238         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 239 #endif
 240 #ifdef CONFIG_SYS_GPIO2_PRELIM
 241         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 242         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 243 #endif
 244 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
 245         uint32_t temp;
 246         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 247
 248         /* Configure interface. */
 249         setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 250
 251         /* Wait for clock to stabilize */
 252         do {
 253                 temp = __raw_readl(&ehci->control);
 254                 udelay(1000);
 255         } while (!(temp & PHY_CLK_VALID));
 256 #endif
 257 }
 258
 259 int cpu_init_r (void)
 260 {
 261 #ifdef CONFIG_QE
 262         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 263
 264         qe_init(qe_base);
 265         qe_reset();
 266 #endif
 267         return 0;
 268 }
 269
 270 /*
 271  * Print out the bus arbiter event
 272  */
 273 #if defined(CONFIG_DISPLAY_AER_FULL)
 274 static int print_83xx_arb_event(int force)
 275 {
 276         static char* event[] = {
 277                 "Address Time Out",
 278                 "Data Time Out",
 279                 "Address Only Transfer Type",
 280                 "External Control Word Transfer Type",
 281                 "Reserved Transfer Type",
 282                 "Transfer Error",
 283                 "reserved",
 284                 "reserved"
 285         };
 286         static char* master[] = {
 287                 "e300 Core Data Transaction",
 288                 "reserved",
 289                 "e300 Core Instruction Fetch",
 290                 "reserved",
 291                 "TSEC1",
 292                 "TSEC2",
 293                 "USB MPH",
 294                 "USB DR",
 295                 "Encryption Core",
 296                 "I2C Boot Sequencer",
 297                 "JTAG",
 298                 "reserved",
 299                 "eSDHC",
 300                 "PCI1",
 301                 "PCI2",
 302                 "DMA",
 303                 "QUICC Engine 00",
 304                 "QUICC Engine 01",
 305                 "QUICC Engine 10",
 306                 "QUICC Engine 11",
 307                 "reserved",
 308                 "reserved",
 309                 "reserved",
 310                 "reserved",
 311                 "SATA1",
 312                 "SATA2",
 313                 "SATA3",
 314                 "SATA4",
 315                 "reserved",
 316                 "PCI Express 1",
 317                 "PCI Express 2",
 318                 "TDM-DMAC"
 319         };
 320         static char *transfer[] = {
 321                 "Address-only, Clean Block",
 322                 "Address-only, lwarx reservation set",
 323                 "Single-beat or Burst write",
 324                 "reserved",
 325                 "Address-only, Flush Block",
 326                 "reserved",
 327                 "Burst write",
 328                 "reserved",
 329                 "Address-only, sync",
 330                 "Address-only, tlbsync",
 331                 "Single-beat or Burst read",
 332                 "Single-beat or Burst read",
 333                 "Address-only, Kill Block",
 334                 "Address-only, icbi",
 335                 "Burst read",
 336                 "reserved",
 337                 "Address-only, eieio",
 338                 "reserved",
 339                 "Single-beat write",
 340                 "reserved",
 341                 "ecowx - Illegal single-beat write",
 342                 "reserved",
 343                 "reserved",
 344                 "reserved",
 345                 "Address-only, TLB Invalidate",
 346                 "reserved",
 347                 "Single-beat or Burst read",
 348                 "reserved",
 349                 "eciwx - Illegal single-beat read",
 350                 "reserved",
 351                 "Burst read",
 352                 "reserved"
 353         };
 354
 355         int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
 356                     >> AEATR_EVENT_SHIFT;
 357         int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
 358                       >> AEATR_MSTR_ID_SHIFT;
 359         int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
 360                    >> AEATR_TBST_SHIFT;
 361         int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
 362                     >> AEATR_TSIZE_SHIFT;
 363         int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
 364                     >> AEATR_TTYPE_SHIFT;
 365
 366         if (!force && !gd->arch.arbiter_event_address)
 367                 return 0;
 368
 369         puts("Arbiter Event Status:\n");
 370         printf("       Event Address: 0x%08lX\n",
 371                gd->arch.arbiter_event_address);
 372         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 373         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 374         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 375                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 376         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 377
 378         return gd->arch.arbiter_event_address;
 379 }
 380
 381 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 382
 383 static int print_83xx_arb_event(int force)
 384 {
 385         if (!force && !gd->arch.arbiter_event_address)
 386                 return 0;
 387
 388         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 389                 gd->arch.arbiter_event_attributes,
 390                 gd->arch.arbiter_event_address);
 391
 392         return gd->arch.arbiter_event_address;
 393 }
 394 #endif /* CONFIG_DISPLAY_AER_xxxx */
 395
 396 #ifndef CONFIG_CPU_MPC83XX
 397 /*
 398  * Figure out the cause of the reset
 399  */
 400 int prt_83xx_rsr(void)
 401 {
 402         static struct {
 403                 ulong mask;
 404                 char *desc;
 405         } bits[] = {
 406                 {
 407                 RSR_SWSR, "Software Soft"}, {
 408                 RSR_SWHR, "Software Hard"}, {
 409                 RSR_JSRS, "JTAG Soft"}, {
 410                 RSR_CSHR, "Check Stop"}, {
 411                 RSR_SWRS, "Software Watchdog"}, {
 412                 RSR_BMRS, "Bus Monitor"}, {
 413                 RSR_SRS,  "External/Internal Soft"}, {
 414                 RSR_HRS,  "External/Internal Hard"}
 415         };
 416         static int n = ARRAY_SIZE(bits);
 417         ulong rsr = gd->arch.reset_status;
 418         int i;
 419         char *sep;
 420
 421         puts("Reset Status:");
 422
 423         sep = " ";
 424         for (i = 0; i < n; i++)
 425                 if (rsr & bits[i].mask) {
 426                         printf("%s%s", sep, bits[i].desc);
 427                         sep = ", ";
 428                 }
 429         puts("\n");
 430
 431 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 432         print_83xx_arb_event(rsr & RSR_BMRS);
 433 #endif
 434         puts("\n");
 435
 436         return 0;
 437 }
 438 #endif