arch/powerpc/cpu/mpc83xx/cpu.c

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * CPU specific code for the MPC83xx family.
   9  *
  10  * Derived from the MPC8260 and MPC85xx.
  11  */
  12
  13 #include <common.h>
  14 #include <watchdog.h>
  15 #include <command.h>
  16 #include <mpc83xx.h>
  17 #include <asm/processor.h>
  18 #include <linux/libfdt.h>
  19 #include <tsec.h>
  20 #include <netdev.h>
  21 #include <fsl_esdhc.h>
  22 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
  23 #include <linux/immap_qe.h>
  24 #include <asm/io.h>
  25 #endif
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int checkcpu(void)
  30 {
  31         volatile immap_t *immr;
  32         ulong clock = gd->cpu_clk;
  33         u32 pvr = get_pvr();
  34         u32 spridr;
  35         char buf[32];
  36         int ret;
  37         int i;
  38
  39         const struct cpu_type {
  40                 char name[15];
  41                 u32 partid;
  42         } cpu_type_list [] = {
  43                 CPU_TYPE_ENTRY(8308),
  44                 CPU_TYPE_ENTRY(8309),
  45                 CPU_TYPE_ENTRY(8311),
  46                 CPU_TYPE_ENTRY(8313),
  47                 CPU_TYPE_ENTRY(8314),
  48                 CPU_TYPE_ENTRY(8315),
  49                 CPU_TYPE_ENTRY(8321),
  50                 CPU_TYPE_ENTRY(8323),
  51                 CPU_TYPE_ENTRY(8343),
  52                 CPU_TYPE_ENTRY(8347_TBGA_),
  53                 CPU_TYPE_ENTRY(8347_PBGA_),
  54                 CPU_TYPE_ENTRY(8349),
  55                 CPU_TYPE_ENTRY(8358_TBGA_),
  56                 CPU_TYPE_ENTRY(8358_PBGA_),
  57                 CPU_TYPE_ENTRY(8360),
  58                 CPU_TYPE_ENTRY(8377),
  59                 CPU_TYPE_ENTRY(8378),
  60                 CPU_TYPE_ENTRY(8379),
  61         };
  62
  63         immr = (immap_t *)CONFIG_SYS_IMMR;
  64
  65         ret = prt_83xx_rsr();
  66         if (ret)
  67                 return ret;
  68
  69         puts("CPU:   ");
  70
  71         switch (pvr & 0xffff0000) {
  72                 case PVR_E300C1:
  73                         printf("e300c1, ");
  74                         break;
  75
  76                 case PVR_E300C2:
  77                         printf("e300c2, ");
  78                         break;
  79
  80                 case PVR_E300C3:
  81                         printf("e300c3, ");
  82                         break;
  83
  84                 case PVR_E300C4:
  85                         printf("e300c4, ");
  86                         break;
  87
  88                 default:
  89                         printf("Unknown core, ");
  90         }
  91
  92         spridr = immr->sysconf.spridr;
  93
  94         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  95                 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
  96                         puts("MPC");
  97                         puts(cpu_type_list[i].name);
  98                         if (IS_E_PROCESSOR(spridr))
  99                                 puts("E");
 100                         if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
 101                              SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
 102                             REVID_MAJOR(spridr) >= 2)
 103                                 puts("A");
 104                         printf(", Rev: %d.%d", REVID_MAJOR(spridr),
 105                                REVID_MINOR(spridr));
 106                         break;
 107                 }
 108
 109         if (i == ARRAY_SIZE(cpu_type_list))
 110                 printf("(SPRIDR %08x unknown), ", spridr);
 111
 112         printf(" at %s MHz, ", strmhz(buf, clock));
 113
 114         printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
 115
 116         return 0;
 117 }
 118
 119 int
 120 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 121 {
 122         ulong msr;
 123 #ifndef MPC83xx_RESET
 124         ulong addr;
 125 #endif
 126
 127         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 128
 129         puts("Resetting the board.\n");
 130
 131 #ifdef MPC83xx_RESET
 132
 133         /* Interrupts and MMU off */
 134         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 135
 136         msr &= ~( MSR_EE | MSR_IR | MSR_DR);
 137         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 138
 139         /* enable Reset Control Reg */
 140         immap->reset.rpr = 0x52535445;
 141         __asm__ __volatile__ ("sync");
 142         __asm__ __volatile__ ("isync");
 143
 144         /* confirm Reset Control Reg is enabled */
 145         while(!((immap->reset.rcer) & RCER_CRE));
 146
 147         udelay(200);
 148
 149         /* perform reset, only one bit */
 150         immap->reset.rcr = RCR_SWHR;
 151
 152 #else   /* ! MPC83xx_RESET */
 153
 154         immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */
 155
 156         /* Interrupts and MMU off */
 157         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 158
 159         msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 160         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 161
 162         /*
 163          * Trying to execute the next instruction at a non-existing address
 164          * should cause a machine check, resulting in reset
 165          */
 166         addr = CONFIG_SYS_RESET_ADDRESS;
 167
 168         ((void (*)(void)) addr) ();
 169 #endif  /* MPC83xx_RESET */
 170
 171         return 1;
 172 }
 173
 174
 175 /*
 176  * Get timebase clock frequency (like cpu_clk in Hz)
 177  */
 178
 179 unsigned long get_tbclk(void)
 180 {
 181         return (gd->bus_clk + 3L) / 4L;
 182 }
 183
 184
 185 #if defined(CONFIG_WATCHDOG)
 186 void watchdog_reset (void)
 187 {
 188         int re_enable = disable_interrupts();
 189
 190         /* Reset the 83xx watchdog */
 191         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 192         immr->wdt.swsrr = 0x556c;
 193         immr->wdt.swsrr = 0xaa39;
 194
 195         if (re_enable)
 196                 enable_interrupts ();
 197 }
 198 #endif
 199
 200 /*
 201  * Initializes on-chip ethernet controllers.
 202  * to override, implement board_eth_init()
 203  */
 204 int cpu_eth_init(bd_t *bis)
 205 {
 206 #if defined(CONFIG_UEC_ETH)
 207         uec_standard_init(bis);
 208 #endif
 209
 210 #if defined(CONFIG_TSEC_ENET)
 211         tsec_standard_init(bis);
 212 #endif
 213         return 0;
 214 }
 215
 216 /*
 217  * Initializes on-chip MMC controllers.
 218  * to override, implement board_mmc_init()
 219  */
 220 int cpu_mmc_init(bd_t *bis)
 221 {
 222 #ifdef CONFIG_FSL_ESDHC
 223         return fsl_esdhc_mmc_init(bis);
 224 #else
 225         return 0;
 226 #endif
 227 }