1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * CPU specific code for the MPC83xx family.
9 * Derived from the MPC8260 and MPC85xx.
21 #include <asm/processor.h>
22 #include <linux/delay.h>
23 #include <linux/libfdt.h>
26 #include <fsl_esdhc.h>
27 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
28 #include <linux/immap_qe.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #ifndef CONFIG_CPU_MPC83XX
37 volatile immap_t *immr;
38 ulong clock = gd->cpu_clk;
45 const struct cpu_type {
48 } cpu_type_list [] = {
58 CPU_TYPE_ENTRY(8347_TBGA_),
59 CPU_TYPE_ENTRY(8347_PBGA_),
61 CPU_TYPE_ENTRY(8358_TBGA_),
62 CPU_TYPE_ENTRY(8358_PBGA_),
69 immr = (immap_t *)CONFIG_SYS_IMMR;
77 switch (pvr & 0xffff0000) {
95 printf("Unknown core, ");
98 spridr = immr->sysconf.spridr;
100 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
101 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
103 puts(cpu_type_list[i].name);
104 if (IS_E_PROCESSOR(spridr))
106 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
107 SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
108 REVID_MAJOR(spridr) >= 2)
110 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
111 REVID_MINOR(spridr));
115 if (i == ARRAY_SIZE(cpu_type_list))
116 printf("(SPRIDR %08x unknown), ", spridr);
118 printf(" at %s MHz, ", strmhz(buf, clock));
120 printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
126 #ifndef CONFIG_SYSRESET
127 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
130 #ifndef MPC83xx_RESET
134 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
136 puts("Resetting the board.\n");
140 /* Interrupts and MMU off */
142 msr &= ~(MSR_EE | MSR_IR | MSR_DR);
145 /* enable Reset Control Reg */
146 immap->reset.rpr = 0x52535445;
150 /* confirm Reset Control Reg is enabled */
151 while(!((immap->reset.rcer) & RCER_CRE))
156 /* perform reset, only one bit */
157 immap->reset.rcr = RCR_SWHR;
159 #else /* ! MPC83xx_RESET */
161 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
163 /* Interrupts and MMU off */
165 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
169 * Trying to execute the next instruction at a non-existing address
170 * should cause a machine check, resulting in reset
172 addr = CONFIG_SYS_RESET_ADDRESS;
174 ((void (*)(void)) addr) ();
175 #endif /* MPC83xx_RESET */
182 * Get timebase clock frequency (like cpu_clk in Hz)
185 unsigned long get_tbclk(void)
187 return (gd->bus_clk + 3L) / 4L;
191 #if defined(CONFIG_WATCHDOG)
192 void watchdog_reset (void)
194 int re_enable = disable_interrupts();
196 /* Reset the 83xx watchdog */
197 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
198 immr->wdt.swsrr = 0x556c;
199 immr->wdt.swsrr = 0xaa39;
206 #ifndef CONFIG_DM_ETH
208 * Initializes on-chip ethernet controllers.
209 * to override, implement board_eth_init()
211 int cpu_eth_init(bd_t *bis)
213 #if defined(CONFIG_UEC_ETH)
214 uec_standard_init(bis);
217 #if defined(CONFIG_TSEC_ENET)
218 tsec_standard_init(bis);
222 #endif /* !CONFIG_DM_ETH */
225 * Initializes on-chip MMC controllers.
226 * to override, implement board_mmc_init()
228 int cpu_mmc_init(bd_t *bis)
230 #ifdef CONFIG_FSL_ESDHC
231 return fsl_esdhc_mmc_init(bis);
237 void ppcDWstore(unsigned int *addr, unsigned int *value)
239 asm("lfd 1, 0(%1)\n\t"
242 : "r" (addr), "r" (value)
246 void ppcDWload(unsigned int *addr, unsigned int *ret)
248 asm("lfd 1, 0(%0)\n\t"
251 : "r" (addr), "r" (ret)