arch/powerpc/cpu/mpc83xx/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * CPU specific code for the MPC83xx family.
   8  *
   9  * Derived from the MPC8260 and MPC85xx.
  10  */
  11
  12 #include <common.h>
  13 #include <cpu_func.h>
  14 #include <irq_func.h>
  15 #include <net.h>
  16 #include <time.h>
  17 #include <vsprintf.h>
  18 #include <watchdog.h>
  19 #include <command.h>
  20 #include <mpc83xx.h>
  21 #include <asm/processor.h>
  22 #include <linux/delay.h>
  23 #include <linux/libfdt.h>
  24 #include <tsec.h>
  25 #include <netdev.h>
  26 #include <fsl_esdhc.h>
  27 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
  28 #include <linux/immap_qe.h>
  29 #include <asm/io.h>
  30 #endif
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #ifndef CONFIG_CPU_MPC83XX
  35 int checkcpu(void)
  36 {
  37         volatile immap_t *immr;
  38         ulong clock = gd->cpu_clk;
  39         u32 pvr = get_pvr();
  40         u32 spridr;
  41         char buf[32];
  42         int ret;
  43         int i;
  44
  45         const struct cpu_type {
  46                 char name[15];
  47                 u32 partid;
  48         } cpu_type_list [] = {
  49                 CPU_TYPE_ENTRY(8308),
  50                 CPU_TYPE_ENTRY(8309),
  51                 CPU_TYPE_ENTRY(8311),
  52                 CPU_TYPE_ENTRY(8313),
  53                 CPU_TYPE_ENTRY(8314),
  54                 CPU_TYPE_ENTRY(8315),
  55                 CPU_TYPE_ENTRY(8321),
  56                 CPU_TYPE_ENTRY(8323),
  57                 CPU_TYPE_ENTRY(8343),
  58                 CPU_TYPE_ENTRY(8347_TBGA_),
  59                 CPU_TYPE_ENTRY(8347_PBGA_),
  60                 CPU_TYPE_ENTRY(8349),
  61                 CPU_TYPE_ENTRY(8358_TBGA_),
  62                 CPU_TYPE_ENTRY(8358_PBGA_),
  63                 CPU_TYPE_ENTRY(8360),
  64                 CPU_TYPE_ENTRY(8377),
  65                 CPU_TYPE_ENTRY(8378),
  66                 CPU_TYPE_ENTRY(8379),
  67         };
  68
  69         immr = (immap_t *)CONFIG_SYS_IMMR;
  70
  71         ret = prt_83xx_rsr();
  72         if (ret)
  73                 return ret;
  74
  75         puts("CPU:   ");
  76
  77         switch (pvr & 0xffff0000) {
  78                 case PVR_E300C1:
  79                         printf("e300c1, ");
  80                         break;
  81
  82                 case PVR_E300C2:
  83                         printf("e300c2, ");
  84                         break;
  85
  86                 case PVR_E300C3:
  87                         printf("e300c3, ");
  88                         break;
  89
  90                 case PVR_E300C4:
  91                         printf("e300c4, ");
  92                         break;
  93
  94                 default:
  95                         printf("Unknown core, ");
  96         }
  97
  98         spridr = immr->sysconf.spridr;
  99
 100         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 101                 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
 102                         puts("MPC");
 103                         puts(cpu_type_list[i].name);
 104                         if (IS_E_PROCESSOR(spridr))
 105                                 puts("E");
 106                         if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
 107                              SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
 108                             REVID_MAJOR(spridr) >= 2)
 109                                 puts("A");
 110                         printf(", Rev: %d.%d", REVID_MAJOR(spridr),
 111                                REVID_MINOR(spridr));
 112                         break;
 113                 }
 114
 115         if (i == ARRAY_SIZE(cpu_type_list))
 116                 printf("(SPRIDR %08x unknown), ", spridr);
 117
 118         printf(" at %s MHz, ", strmhz(buf, clock));
 119
 120         printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
 121
 122         return 0;
 123 }
 124 #endif
 125
 126 #ifndef CONFIG_SYSRESET
 127 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 128 {
 129         ulong msr;
 130         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 131
 132         puts("Resetting the board.\n");
 133
 134         /* Interrupts and MMU off */
 135         msr = mfmsr();
 136         msr &= ~(MSR_EE | MSR_IR | MSR_DR);
 137         mtmsr(msr);
 138
 139         /* enable Reset Control Reg */
 140         immap->reset.rpr = 0x52535445;
 141         sync();
 142         isync();
 143
 144         /* confirm Reset Control Reg is enabled */
 145         while(!((immap->reset.rcer) & RCER_CRE))
 146                 ;
 147
 148         udelay(200);
 149
 150         /* perform reset, only one bit */
 151         immap->reset.rcr = RCR_SWHR;
 152
 153         return 1;
 154 }
 155 #endif
 156
 157 /*
 158  * Get timebase clock frequency (like cpu_clk in Hz)
 159  */
 160 #ifndef CONFIG_TIMER
 161 unsigned long get_tbclk(void)
 162 {
 163         return (gd->bus_clk + 3L) / 4L;
 164 }
 165 #endif
 166
 167 #if defined(CONFIG_WATCHDOG)
 168 void watchdog_reset (void)
 169 {
 170         int re_enable = disable_interrupts();
 171
 172         /* Reset the 83xx watchdog */
 173         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 174         immr->wdt.swsrr = 0x556c;
 175         immr->wdt.swsrr = 0xaa39;
 176
 177         if (re_enable)
 178                 enable_interrupts();
 179 }
 180 #endif
 181
 182 #ifndef CONFIG_DM_ETH
 183 /*
 184  * Initializes on-chip ethernet controllers.
 185  * to override, implement board_eth_init()
 186  */
 187 int cpu_eth_init(bd_t *bis)
 188 {
 189 #if defined(CONFIG_UEC_ETH)
 190         uec_standard_init(bis);
 191 #endif
 192
 193 #if defined(CONFIG_TSEC_ENET)
 194         tsec_standard_init(bis);
 195 #endif
 196         return 0;
 197 }
 198 #endif /* !CONFIG_DM_ETH */
 199
 200 /*
 201  * Initializes on-chip MMC controllers.
 202  * to override, implement board_mmc_init()
 203  */
 204 int cpu_mmc_init(bd_t *bis)
 205 {
 206 #ifdef CONFIG_FSL_ESDHC
 207         return fsl_esdhc_mmc_init(bis);
 208 #else
 209         return 0;
 210 #endif
 211 }
 212
 213 void ppcDWstore(unsigned int *addr, unsigned int *value)
 214 {
 215         asm("lfd 1, 0(%1)\n\t"
 216             "stfd 1, 0(%0)"
 217             :
 218             : "r" (addr), "r" (value)
 219             : "memory");
 220 }
 221
 222 void ppcDWload(unsigned int *addr, unsigned int *ret)
 223 {
 224         asm("lfd 1, 0(%0)\n\t"
 225             "stfd 1, 0(%1)"
 226             :
 227             : "r" (addr), "r" (ret)
 228             : "memory");
 229 }