arch/mips/mach-mtmips/mt7628/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020 MediaTek Inc.
   4  *
   5  * Author:  Weijie Gao <weijie.gao@mediatek.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/addrspace.h>
  10 #include <linux/bitops.h>
  11 #include <linux/sizes.h>
  12 #include <linux/io.h>
  13 #include <mach/ddr.h>
  14 #include <mach/mc.h>
  15 #include "mt7628.h"
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 /* DDR2 DQ_DLY */
  20 #define DDR2_DQ_DLY \
  21                                 ((0x8 << DQ1_DELAY_COARSE_TUNING_S) | \
  22                                 (0x2 << DQ1_DELAY_FINE_TUNING_S) | \
  23                                 (0x8 << DQ0_DELAY_COARSE_TUNING_S) | \
  24                                 (0x2 << DQ0_DELAY_FINE_TUNING_S))
  25
  26 /* DDR2 DQS_DLY */
  27 #define DDR2_DQS_DLY \
  28                                 ((0x8 << DQS1_DELAY_COARSE_TUNING_S) | \
  29                                 (0x3 << DQS1_DELAY_FINE_TUNING_S) | \
  30                                 (0x8 << DQS0_DELAY_COARSE_TUNING_S) | \
  31                                 (0x3 << DQS0_DELAY_FINE_TUNING_S))
  32
  33 const struct mc_ddr_cfg ddr1_cfgs_200mhz[] = {
  34         [DRAM_8MB]   = { 0x34A1EB94, 0x20262324, 0x28000033, 0x00000002, 0x00000000 },
  35         [DRAM_16MB]  = { 0x34A1EB94, 0x202A2324, 0x28000033, 0x00000002, 0x00000000 },
  36         [DRAM_32MB]  = { 0x34A1E5CA, 0x202E2324, 0x28000033, 0x00000002, 0x00000000 },
  37         [DRAM_64MB]  = { 0x3421E5CA, 0x20322324, 0x28000033, 0x00000002, 0x00000000 },
  38         [DRAM_128MB] = { 0x241B05CA, 0x20362334, 0x28000033, 0x00000002, 0x00000000 },
  39 };
  40
  41 const struct mc_ddr_cfg ddr1_cfgs_160mhz[] = {
  42         [DRAM_8MB]   = { 0x239964A1, 0x20262323, 0x00000033, 0x00000002, 0x00000000 },
  43         [DRAM_16MB]  = { 0x239964A1, 0x202A2323, 0x00000033, 0x00000002, 0x00000000 },
  44         [DRAM_32MB]  = { 0x239964A1, 0x202E2323, 0x00000033, 0x00000002, 0x00000000 },
  45         [DRAM_64MB]  = { 0x239984A1, 0x20322323, 0x00000033, 0x00000002, 0x00000000 },
  46         [DRAM_128MB] = { 0x239AB4A1, 0x20362333, 0x00000033, 0x00000002, 0x00000000 },
  47 };
  48
  49 const struct mc_ddr_cfg ddr2_cfgs_200mhz[] = {
  50         [DRAM_32MB]  = { 0x2519E2E5, 0x222E2323, 0x68000C43, 0x00000452, 0x0000000A },
  51         [DRAM_64MB]  = { 0x249AA2E5, 0x22322323, 0x68000C43, 0x00000452, 0x0000000A },
  52         [DRAM_128MB] = { 0x249B42E5, 0x22362323, 0x68000C43, 0x00000452, 0x0000000A },
  53         [DRAM_256MB] = { 0x249CE2E5, 0x223A2323, 0x68000C43, 0x00000452, 0x0000000A },
  54 };
  55
  56 const struct mc_ddr_cfg ddr2_cfgs_160mhz[] = {
  57         [DRAM_32MB]  = { 0x23918250, 0x222E2322, 0x40000A43, 0x00000452, 0x00000006 },
  58         [DRAM_64MB]  = { 0x239A2250, 0x22322322, 0x40000A43, 0x00000452, 0x00000008 },
  59         [DRAM_128MB] = { 0x2392A250, 0x22362322, 0x40000A43, 0x00000452, 0x00000008 },
  60         [DRAM_256MB] = { 0x24140250, 0x223A2322, 0x40000A43, 0x00000452, 0x00000008 },
  61 };
  62
  63 static void mt7628_memc_reset(int assert)
  64 {
  65         void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
  66
  67         if (assert)
  68                 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST);
  69         else
  70                 clrbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST);
  71 }
  72
  73 static void mt7628_ddr_pad_ldo_config(int ddr_type, int pkg_type)
  74 {
  75         void __iomem *rgc = ioremap_nocache(RGCTL_BASE, RGCTL_SIZE);
  76         u32 ck_pad1, cmd_pad1, dq_pad0, dq_pad1, dqs_pad0, dqs_pad1;
  77
  78         setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN);
  79
  80         if (ddr_type == DRAM_DDR1)
  81                 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL);
  82         else
  83                 clrbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL);
  84
  85         setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN);
  86
  87         __udelay(250 * 50);
  88
  89         setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB);
  90         setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM);
  91
  92         ck_pad1 = readl(rgc + RGCTL_DDR_PAD_CK_G1_REG);
  93         cmd_pad1 = readl(rgc + RGCTL_DDR_PAD_CMD_G1_REG);
  94         dq_pad0 = readl(rgc + RGCTL_DDR_PAD_DQ_G0_REG);
  95         dq_pad1 = readl(rgc + RGCTL_DDR_PAD_DQ_G1_REG);
  96         dqs_pad0 = readl(rgc + RGCTL_DDR_PAD_DQS_G0_REG);
  97         dqs_pad1 = readl(rgc + RGCTL_DDR_PAD_DQS_G1_REG);
  98
  99         ck_pad1 &= ~(DRVP_M | DRVN_M);
 100         cmd_pad1 &= ~(DRVP_M | DRVN_M);
 101         dq_pad0 &= ~RTT_M;
 102         dq_pad1 &= ~(DRVP_M | DRVN_M);
 103         dqs_pad0 &= ~RTT_M;
 104         dqs_pad1 &= ~(DRVP_M | DRVN_M);
 105
 106         if (pkg_type == PKG_ID_KN) {
 107                 ck_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
 108                 cmd_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
 109                 dq_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
 110                 dqs_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
 111         } else {
 112                 ck_pad1 |= (12 << DRVP_S) | (12 << DRVN_S);
 113                 cmd_pad1 |= (2 << DRVP_S) | (2 << DRVN_S);
 114                 dqs_pad1 |= (12 << DRVP_S) | (12 << DRVN_S);
 115                 if (ddr_type == DRAM_DDR1)
 116                         dq_pad1 |= (7 << DRVP_S) | (7 << DRVN_S);
 117                 else
 118                         dq_pad1 |= (4 << DRVP_S) | (4 << DRVN_S);
 119         }
 120
 121         writel(ck_pad1, rgc + RGCTL_DDR_PAD_CK_G1_REG);
 122         writel(cmd_pad1, rgc + RGCTL_DDR_PAD_CMD_G1_REG);
 123         writel(dq_pad0, rgc + RGCTL_DDR_PAD_DQ_G0_REG);
 124         writel(dq_pad1, rgc + RGCTL_DDR_PAD_DQ_G1_REG);
 125         writel(dqs_pad0, rgc + RGCTL_DDR_PAD_DQS_G0_REG);
 126         writel(dqs_pad1, rgc + RGCTL_DDR_PAD_DQS_G1_REG);
 127 }
 128
 129 void mt7628_ddr_init(void)
 130 {
 131         void __iomem *sysc;
 132         int ddr_type, pkg_type, lspd;
 133         struct mc_ddr_init_param param;
 134
 135         sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
 136         ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE;
 137         pkg_type = !!(readl(sysc + SYSCTL_CHIP_REV_ID_REG) & PKG_ID);
 138         lspd = readl(sysc + SYSCTL_CLKCFG0_REG) &
 139                (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL);
 140
 141         mt7628_memc_reset(1);
 142         __udelay(200);
 143
 144         mt7628_ddr_pad_ldo_config(ddr_type, pkg_type);
 145
 146         param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE);
 147         param.dq_dly = DDR2_DQ_DLY;
 148         param.dqs_dly = DDR2_DQS_DLY;
 149         param.mc_reset = mt7628_memc_reset;
 150         param.memsize = 0;
 151         param.bus_width = 0;
 152
 153         if (pkg_type == PKG_ID_KN)
 154                 ddr_type = DRAM_DDR1;
 155
 156         if (ddr_type == DRAM_DDR1) {
 157                 if (lspd)
 158                         param.cfgs = ddr1_cfgs_160mhz;
 159                 else
 160                         param.cfgs = ddr1_cfgs_200mhz;
 161                 ddr1_init(&param);
 162         } else {
 163                 if (lspd)
 164                         param.cfgs = ddr2_cfgs_160mhz;
 165                 else
 166                         param.cfgs = ddr2_cfgs_200mhz;
 167                 ddr2_init(&param);
 168         }
 169
 170         ddr_calibrate(param.memc, param.memsize, param.bus_width);
 171
 172         gd->ram_size = param.memsize;
 173 }