arch/mips/mach-jz47xx/jz4780/pll.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * JZ4780 PLL setup
   4  *
   5  * Copyright (c) 2013 Imagination Technologies
   6  * Author: Paul Burton <paul.burton@imgtec.com>
   7  */
   8
   9 #include <config.h>
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <linux/delay.h>
  13 #include <mach/jz4780.h>
  14
  15 #define CPM_CPCCR               0x00
  16 #define CPM_LCR                 0x04
  17 #define CPM_RSR                 0x08
  18 #define CPM_CPPCR               0x0c
  19 #define CPM_CPAPCR              0x10
  20 #define CPM_CPMPCR              0x14
  21 #define CPM_CPEPCR              0x18
  22 #define CPM_CPVPCR              0x1c
  23 #define CPM_CLKGR0              0x20
  24 #define CPM_OPCR                0x24
  25 #define CPM_CLKGR1              0x28
  26 #define CPM_DDCDR               0x2c
  27 #define CPM_VPUCDR              0x30
  28 #define CPM_CPSPR               0x34
  29 #define CPM_CPSPPR              0x38
  30 #define CPM_USBPCR              0x3c
  31 #define CPM_USBRDT              0x40
  32 #define CPM_USBVBFIL            0x44
  33 #define CPM_USBPCR1             0x48
  34 #define CPM_USBCDR              0x50
  35 #define CPM_LPCDR               0x54
  36 #define CPM_I2SCDR              0x60
  37 #define CPM_LPCDR1              0x64
  38 #define CPM_MSCCDR              0x68
  39 #define CPM_UHCCDR              0x6c
  40 #define CPM_SSICDR              0x74
  41 #define CPM_CIMCDR              0x7c
  42 #define CPM_PCMCDR              0x84
  43 #define CPM_GPUCDR              0x88
  44 #define CPM_HDMICDR             0x8c
  45 #define CPM_I2S1CDR             0xa0
  46 #define CPM_MSCCDR1             0xa4
  47 #define CPM_MSCCDR2             0xa8
  48 #define CPM_BCHCDR              0xac
  49 #define CPM_SPCR0               0xb8
  50 #define CPM_SPCR1               0xbc
  51 #define CPM_CPCSR               0xd4
  52 #define CPM_PSWCST(n)           ((0x4 * (n)) + 0x90)
  53
  54 /* Clock control register */
  55 #define CPM_CPCCR_SEL_SRC_BIT           30
  56 #define CPM_CPCCR_SEL_SRC_MASK          (0x3 << CPM_CPCCR_SEL_SRC_BIT)
  57 #define CPM_SRC_SEL_STOP                0
  58 #define CPM_SRC_SEL_APLL                1
  59 #define CPM_SRC_SEL_EXCLK               2
  60 #define CPM_SRC_SEL_RTCLK               3
  61 #define CPM_CPCCR_SEL_CPLL_BIT          28
  62 #define CPM_CPCCR_SEL_CPLL_MASK         (0x3 << CPM_CPCCR_SEL_CPLL_BIT)
  63 #define CPM_CPCCR_SEL_H0PLL_BIT         26
  64 #define CPM_CPCCR_SEL_H0PLL_MASK        (0x3 << CPM_CPCCR_SEL_H0PLL_BIT)
  65 #define CPM_CPCCR_SEL_H2PLL_BIT         24
  66 #define CPM_CPCCR_SEL_H2PLL_MASK        (0x3 << CPM_CPCCR_SEL_H2PLL_BIT)
  67 #define CPM_PLL_SEL_STOP                0
  68 #define CPM_PLL_SEL_SRC                 1
  69 #define CPM_PLL_SEL_MPLL                2
  70 #define CPM_PLL_SEL_EPLL                3
  71 #define CPM_CPCCR_CE_CPU                (0x1 << 22)
  72 #define CPM_CPCCR_CE_AHB0               (0x1 << 21)
  73 #define CPM_CPCCR_CE_AHB2               (0x1 << 20)
  74 #define CPM_CPCCR_PDIV_BIT              16
  75 #define CPM_CPCCR_PDIV_MASK             (0xf << CPM_CPCCR_PDIV_BIT)
  76 #define CPM_CPCCR_H2DIV_BIT             12
  77 #define CPM_CPCCR_H2DIV_MASK            (0xf << CPM_CPCCR_H2DIV_BIT)
  78 #define CPM_CPCCR_H0DIV_BIT             8
  79 #define CPM_CPCCR_H0DIV_MASK            (0x0f << CPM_CPCCR_H0DIV_BIT)
  80 #define CPM_CPCCR_L2DIV_BIT             4
  81 #define CPM_CPCCR_L2DIV_MASK            (0x0f << CPM_CPCCR_L2DIV_BIT)
  82 #define CPM_CPCCR_CDIV_BIT              0
  83 #define CPM_CPCCR_CDIV_MASK             (0x0f << CPM_CPCCR_CDIV_BIT)
  84
  85 /* Clock Status register */
  86 #define CPM_CPCSR_H2DIV_BUSY            BIT(2)
  87 #define CPM_CPCSR_H0DIV_BUSY            BIT(1)
  88 #define CPM_CPCSR_CDIV_BUSY             BIT(0)
  89
  90 /* PLL control register */
  91 #define CPM_CPPCR_PLLST_BIT             0
  92 #define CPM_CPPCR_PLLST_MASK            (0xff << CPM_CPPCR_PLLST_BIT)
  93
  94 /* XPLL control register */
  95 #define CPM_CPXPCR_XPLLM_BIT            19
  96 #define CPM_CPXPCR_XPLLM_MASK           (0x1fff << CPM_CPXPCR_XPLLM_BIT)
  97 #define CPM_CPXPCR_XPLLN_BIT            13
  98 #define CPM_CPXPCR_XPLLN_MASK           (0x3f << CPM_CPXPCR_XPLLN_BIT)
  99 #define CPM_CPXPCR_XPLLOD_BIT           9
 100 #define CPM_CPXPCR_XPLLOD_MASK          (0xf << CPM_CPXPCR_XPLLOD_BIT)
 101 #define CPM_CPXPCR_XLOCK                BIT(6)
 102 #define CPM_CPXPCR_XPLL_ON              BIT(4)
 103 #define CPM_CPXPCR_XF_MODE              BIT(3)
 104 #define CPM_CPXPCR_XPLLBP               BIT(1)
 105 #define CPM_CPXPCR_XPLLEN               BIT(0)
 106
 107 /* CPM scratch protected register */
 108 #define CPM_CPSPPR_BIT                  0
 109 #define CPM_CPSPPR_MASK                 (0xffff << CPM_CPSPPR_BIT)
 110
 111 /* USB parameter control register */
 112 #define CPM_USBPCR_USB_MODE             BIT(31)  /* 1: OTG, 0: UDC*/
 113 #define CPM_USBPCR_AVLD_REG             BIT(30)
 114 #define CPM_USBPCR_IDPULLUP_MASK_BIT    28
 115 #define CPM_USBPCR_IDPULLUP_MASK_MASK   (0x02 << IDPULLUP_MASK_BIT)
 116 #define CPM_USBPCR_INCR_MASK            BIT(27)
 117 #define CPM_USBPCR_CLK12_EN             BIT(26)
 118 #define CPM_USBPCR_COMMONONN            BIT(25)
 119 #define CPM_USBPCR_VBUSVLDEXT           BIT(24)
 120 #define CPM_USBPCR_VBUSVLDEXTSEL        BIT(23)
 121 #define CPM_USBPCR_POR                  BIT(22)
 122 #define CPM_USBPCR_SIDDQ                BIT(21)
 123 #define CPM_USBPCR_OTG_DISABLE          BIT(20)
 124 #define CPM_USBPCR_COMPDISTUNE_BIT      17
 125 #define CPM_USBPCR_COMPDISTUNE_MASK     (0x07 << COMPDISTUNE_BIT)
 126 #define CPM_USBPCR_OTGTUNE_BIT          14
 127 #define CPM_USBPCR_OTGTUNE_MASK         (0x07 << OTGTUNE_BIT)
 128 #define CPM_USBPCR_SQRXTUNE_BIT         11
 129 #define CPM_USBPCR_SQRXTUNE_MASK        (0x7x << SQRXTUNE_BIT)
 130 #define CPM_USBPCR_TXFSLSTUNE_BIT       7
 131 #define CPM_USBPCR_TXFSLSTUNE_MASK      (0x0f << TXFSLSTUNE_BIT)
 132 #define CPM_USBPCR_TXPREEMPHTUNE        BIT(6)
 133 #define CPM_USBPCR_TXRISETUNE_BIT       4
 134 #define CPM_USBPCR_TXRISETUNE_MASK      (0x03 << TXRISETUNE_BIT)
 135 #define CPM_USBPCR_TXVREFTUNE_BIT       0
 136 #define CPM_USBPCR_TXVREFTUNE_MASK      (0x0f << TXVREFTUNE_BIT)
 137
 138 /* DDR memory clock divider register */
 139 #define CPM_DDRCDR_DCS_BIT              30
 140 #define CPM_DDRCDR_DCS_MASK             (0x3 << CPM_DDRCDR_DCS_BIT)
 141 #define CPM_DDRCDR_DCS_STOP             (0x0 << CPM_DDRCDR_DCS_BIT)
 142 #define CPM_DDRCDR_DCS_SRC              (0x1 << CPM_DDRCDR_DCS_BIT)
 143 #define CPM_DDRCDR_DCS_MPLL             (0x2 << CPM_DDRCDR_DCS_BIT)
 144 #define CPM_DDRCDR_CE_DDR               BIT(29)
 145 #define CPM_DDRCDR_DDR_BUSY             BIT(28)
 146 #define CPM_DDRCDR_DDR_STOP             BIT(27)
 147 #define CPM_DDRCDR_DDRDIV_BIT           0
 148 #define CPM_DDRCDR_DDRDIV_MASK          (0xf << CPM_DDRCDR_DDRDIV_BIT)
 149
 150 /* USB reset detect timer register */
 151 #define CPM_USBRDT_VBFIL_LD_EN          BIT(25)
 152 #define CPM_USBRDT_IDDIG_EN             BIT(24)
 153 #define CPM_USBRDT_IDDIG_REG            BIT(23)
 154 #define CPM_USBRDT_USBRDT_BIT           0
 155 #define CPM_USBRDT_USBRDT_MASK          (0x7fffff << CPM_USBRDT_USBRDT_BIT)
 156
 157 /* USB OTG PHY clock divider register */
 158 #define CPM_USBCDR_UCS                  BIT(31)
 159 #define CPM_USBCDR_UPCS                 BIT(30)
 160 #define CPM_USBCDR_CEUSB                BIT(29)
 161 #define CPM_USBCDR_USB_BUSY             BIT(28)
 162 #define CPM_USBCDR_OTGDIV_BIT           0
 163 #define CPM_USBCDR_OTGDIV_MASK          (0xff << CPM_USBCDR_OTGDIV_BIT)
 164
 165 /* I2S device clock divider register */
 166 #define CPM_I2SCDR_I2CS                 BIT(31)
 167 #define CPM_I2SCDR_I2PCS                BIT(30)
 168 #define CPM_I2SCDR_I2SDIV_BIT           0
 169 #define CPM_I2SCDR_I2SDIV_MASK          (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
 170
 171 /* LCD0 pix clock divider register */
 172 #define CPM_LPCDR_LPCS_BIT              30
 173 #define CPM_LPCDR_LPCS_MASK             (0x3 << CPM_LPCDR_LPCS_BIT)
 174 #define CPM_LPCDR_CELCD                 BIT(28)
 175 #define CPM_LPCDR_LCD_BUSY              BIT(27)
 176 #define CPM_LPCDR_LCD_STOP              BIT(26)
 177 #define CPM_LPCDR_PIXDIV_BIT            0
 178 #define CPM_LPCDR_PIXDIV_MASK           (0xff << CPM_LPCDR_PIXDIV_BIT)
 179
 180 /* MSC clock divider register */
 181 #define CPM_MSCCDR_MPCS_BIT             30
 182 #define CPM_MSCCDR_MPCS_MASK            (3 << CPM_MSCCDR_MPCS_BIT)
 183 #define CPM_MSCCDR_MPCS_STOP            (0x0 << CPM_MSCCDR_MPCS_BIT)
 184 #define CPM_MSCCDR_MPCS_SRC             (0x1 << CPM_MSCCDR_MPCS_BIT)
 185 #define CPM_MSCCDR_MPCS_MPLL            (0x2 << CPM_MSCCDR_MPCS_BIT)
 186 #define CPM_MSCCDR_CE                   BIT(29)
 187 #define CPM_MSCCDR_MSC_BUSY             BIT(28)
 188 #define CPM_MSCCDR_MSC_STOP             BIT(27)
 189 #define CPM_MSCCDR_MSC_CLK0_SEL         BIT(15)
 190 #define CPM_MSCCDR_MSCDIV_BIT           0
 191 #define CPM_MSCCDR_MSCDIV_MASK          (0xff << CPM_MSCCDR_MSCDIV_BIT)
 192
 193 /* UHC 48M clock divider register */
 194 #define CPM_UHCCDR_UHCS_BIT             30
 195 #define CPM_UHCCDR_UHCS_MASK            (0x3 << CPM_UHCCDR_UHCS_BIT)
 196 #define CPM_UHCCDR_UHCS_SRC             (0x0 << CPM_UHCCDR_UHCS_BIT)
 197 #define CPM_UHCCDR_UHCS_MPLL            (0x1 << CPM_UHCCDR_UHCS_BIT)
 198 #define CPM_UHCCDR_UHCS_EPLL            (0x2 << CPM_UHCCDR_UHCS_BIT)
 199 #define CPM_UHCCDR_UHCS_OTG             (0x3 << CPM_UHCCDR_UHCS_BIT)
 200 #define CPM_UHCCDR_CE_UHC               BIT(29)
 201 #define CPM_UHCCDR_UHC_BUSY             BIT(28)
 202 #define CPM_UHCCDR_UHC_STOP             BIT(27)
 203 #define CPM_UHCCDR_UHCDIV_BIT           0
 204 #define CPM_UHCCDR_UHCDIV_MASK          (0xff << CPM_UHCCDR_UHCDIV_BIT)
 205
 206 /* SSI clock divider register */
 207 #define CPM_SSICDR_SCS                  BIT(31)
 208 #define CPM_SSICDR_SSIDIV_BIT           0
 209 #define CPM_SSICDR_SSIDIV_MASK          (0x3f << CPM_SSICDR_SSIDIV_BIT)
 210
 211 /* CIM MCLK clock divider register */
 212 #define CPM_CIMCDR_CIMDIV_BIT           0
 213 #define CPM_CIMCDR_CIMDIV_MASK          (0xff << CPM_CIMCDR_CIMDIV_BIT)
 214
 215 /* GPS clock divider register */
 216 #define CPM_GPSCDR_GPCS                 BIT(31)
 217 #define CPM_GPSCDR_GPSDIV_BIT           0
 218 #define CPM_GSPCDR_GPSDIV_MASK          (0xf << CPM_GPSCDR_GPSDIV_BIT)
 219
 220 /* PCM device clock divider register */
 221 #define CPM_PCMCDR_PCMS                 BIT(31)
 222 #define CPM_PCMCDR_PCMPCS               BIT(30)
 223 #define CPM_PCMCDR_PCMDIV_BIT           0
 224 #define CPM_PCMCDR_PCMDIV_MASK          (0x1ff << CPM_PCMCDR_PCMDIV_BIT)
 225
 226 /* GPU clock divider register */
 227 #define CPM_GPUCDR_GPCS                 BIT(31)
 228 #define CPM_GPUCDR_GPUDIV_BIT           0
 229 #define CPM_GPUCDR_GPUDIV_MASK          (0x7 << CPM_GPUCDR_GPUDIV_BIT)
 230
 231 /* HDMI clock divider register */
 232 #define CPM_HDMICDR_HPCS_BIT            30
 233 #define CPM_HDMICDR_HPCS_MASK           (0x3 << CPM_HDMICDR_HPCS_BIT)
 234 #define CPM_HDMICDR_CEHDMI              BIT(29)
 235 #define CPM_HDMICDR_HDMI_BUSY           BIT(28)
 236 #define CPM_HDMICDR_HDMI_STOP           BIT(26)
 237 #define CPM_HDMICDR_HDMIDIV_BIT         0
 238 #define CPM_HDMICDR_HDMIDIV_MASK        (0xff << CPM_HDMICDR_HDMIDIV_BIT)
 239
 240 /* Low Power Control Register */
 241 #define CPM_LCR_PD_SCPU                 BIT(31)
 242 #define CPM_LCR_PD_VPU                  BIT(30)
 243 #define CPM_LCR_PD_GPU                  BIT(29)
 244 #define CPM_LCR_PD_GPS                  BIT(28)
 245 #define CPM_LCR_SCPUS                   BIT(27)
 246 #define CPM_LCR_VPUS                    BIT(26)
 247 #define CPM_LCR_GPUS                    BIT(25)
 248 #define CPM_LCR_GPSS                    BIT(24)
 249 #define CPM_LCR_GPU_IDLE                BIT(20)
 250 #define CPM_LCR_PST_BIT                 8
 251 #define CPM_LCR_PST_MASK                (0xfff << CPM_LCR_PST_BIT)
 252 #define CPM_LCR_DOZE_DUTY_BIT           3
 253 #define CPM_LCR_DOZE_DUTY_MASK          (0x1f << CPM_LCR_DOZE_DUTY_BIT)
 254 #define CPM_LCR_DOZE_ON                 BIT(2)
 255 #define CPM_LCR_LPM_BIT                 0
 256 #define CPM_LCR_LPM_MASK                (0x3 << CPM_LCR_LPM_BIT)
 257 #define CPM_LCR_LPM_IDLE                (0x0 << CPM_LCR_LPM_BIT)
 258 #define CPM_LCR_LPM_SLEEP               (0x1 << CPM_LCR_LPM_BIT)
 259
 260 /* Clock Gate Register0 */
 261 #define CPM_CLKGR0_DDR1                 BIT(31)
 262 #define CPM_CLKGR0_DDR0                 BIT(30)
 263 #define CPM_CLKGR0_IPU                  BIT(29)
 264 #define CPM_CLKGR0_LCD1                 BIT(28)
 265 #define CPM_CLKGR0_LCD                  BIT(27)
 266 #define CPM_CLKGR0_CIM                  BIT(26)
 267 #define CPM_CLKGR0_I2C2                 BIT(25)
 268 #define CPM_CLKGR0_UHC                  BIT(24)
 269 #define CPM_CLKGR0_MAC                  BIT(23)
 270 #define CPM_CLKGR0_GPS                  BIT(22)
 271 #define CPM_CLKGR0_PDMAC                BIT(21)
 272 #define CPM_CLKGR0_SSI2                 BIT(20)
 273 #define CPM_CLKGR0_SSI1                 BIT(19)
 274 #define CPM_CLKGR0_UART3                BIT(18)
 275 #define CPM_CLKGR0_UART2                BIT(17)
 276 #define CPM_CLKGR0_UART1                BIT(16)
 277 #define CPM_CLKGR0_UART0                BIT(15)
 278 #define CPM_CLKGR0_SADC                 BIT(14)
 279 #define CPM_CLKGR0_KBC                  BIT(13)
 280 #define CPM_CLKGR0_MSC2                 BIT(12)
 281 #define CPM_CLKGR0_MSC1                 BIT(11)
 282 #define CPM_CLKGR0_OWI                  BIT(10)
 283 #define CPM_CLKGR0_TSSI                 BIT(9)
 284 #define CPM_CLKGR0_AIC                  BIT(8)
 285 #define CPM_CLKGR0_SCC                  BIT(7)
 286 #define CPM_CLKGR0_I2C1                 BIT(6)
 287 #define CPM_CLKGR0_I2C0                 BIT(5)
 288 #define CPM_CLKGR0_SSI0                 BIT(4)
 289 #define CPM_CLKGR0_MSC0                 BIT(3)
 290 #define CPM_CLKGR0_OTG                  BIT(2)
 291 #define CPM_CLKGR0_BCH                  BIT(1)
 292 #define CPM_CLKGR0_NEMC                 BIT(0)
 293
 294 /* Clock Gate Register1 */
 295 #define CPM_CLKGR1_P1                   BIT(15)
 296 #define CPM_CLKGR1_X2D                  BIT(14)
 297 #define CPM_CLKGR1_DES                  BIT(13)
 298 #define CPM_CLKGR1_I2C4                 BIT(12)
 299 #define CPM_CLKGR1_AHB                  BIT(11)
 300 #define CPM_CLKGR1_UART4                BIT(10)
 301 #define CPM_CLKGR1_HDMI                 BIT(9)
 302 #define CPM_CLKGR1_OTG1                 BIT(8)
 303 #define CPM_CLKGR1_GPVLC                BIT(7)
 304 #define CPM_CLKGR1_AIC1                 BIT(6)
 305 #define CPM_CLKGR1_COMPRES              BIT(5)
 306 #define CPM_CLKGR1_GPU                  BIT(4)
 307 #define CPM_CLKGR1_PCM                  BIT(3)
 308 #define CPM_CLKGR1_VPU                  BIT(2)
 309 #define CPM_CLKGR1_TSSI1                BIT(1)
 310 #define CPM_CLKGR1_I2C3                 BIT(0)
 311
 312 /* Oscillator and Power Control Register */
 313 #define CPM_OPCR_O1ST_BIT               8
 314 #define CPM_OPCR_O1ST_MASK              (0xff << CPM_OPCR_O1ST_BIT)
 315 #define CPM_OPCR_SPENDN                 BIT(7)
 316 #define CPM_OPCR_GPSEN                  BIT(6)
 317 #define CPM_OPCR_SPENDH                 BIT(5)
 318 #define CPM_OPCR_O1SE                   BIT(4)
 319 #define CPM_OPCR_ERCS                   BIT(2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
 320 #define CPM_OPCR_USBM                   BIT(0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
 321
 322 /* Reset Status Register */
 323 #define CPM_RSR_P0R                     BIT(2)
 324 #define CPM_RSR_WR                      BIT(1)
 325 #define CPM_RSR_PR                      BIT(0)
 326
 327 /* BCH clock divider register */
 328 #define CPM_BCHCDR_BPCS_BIT             30
 329 #define CPM_BCHCDR_BPCS_MASK            (0x3 << CPM_BCHCDR_BPCS_BIT)
 330 #define CPM_BCHCDR_BPCS_STOP            (0X0 << CPM_BCHCDR_BPCS_BIT)
 331 #define CPM_BCHCDR_BPCS_SRC_CLK         (0x1 << CPM_BCHCDR_BPCS_BIT)
 332 #define CPM_BCHCDR_BPCS_MPLL            (0x2 << CPM_BCHCDR_BPCS_BIT)
 333 #define CPM_BCHCDR_BPCS_EPLL            (0x3 << CPM_BCHCDR_BPCS_BIT)
 334 #define CPM_BCHCDR_CE_BCH               BIT(29)
 335 #define CPM_BCHCDR_BCH_BUSY             BIT(28)
 336 #define CPM_BCHCDR_BCH_STOP             BIT(27)
 337 #define CPM_BCHCDR_BCHCDR_BIT           0
 338 #define CPM_BCHCDR_BCHCDR_MASK          (0x7 << CPM_BCHCDR_BCHCDR_BIT)
 339
 340 /* CPM scratch pad protected register(CPSPPR) */
 341 #define CPSPPR_CPSPR_WRITABLE           0x00005a5a
 342 #define RECOVERY_SIGNATURE              0x1a1a  /* means "RECY" */
 343 #define RECOVERY_SIGNATURE_SEC          0x800   /* means "RECY" */
 344
 345 #define REBOOT_SIGNATURE                0x3535  /* means reboot */
 346
 347 /* XPLL control register */
 348 #define XLOCK           (1 << 6)
 349 #define XPLL_ON         (1 << 4)
 350 #define XF_MODE         (1 << 3)
 351 #define XPLLBP          (1 << 1)
 352 #define XPLLEN          (1 << 0)
 353
 354 enum PLLS {
 355         EXTCLK = 0,
 356         APLL,
 357         MPLL,
 358         EPLL,
 359         VPLL,
 360 };
 361
 362 #define M_N_OD(m, n, od)                \
 363                 ((((m) - 1) << 19) | (((n) - 1) << 13) | (((od) - 1) << 9))
 364
 365 struct cgu_pll_select {
 366         u8      reg;
 367         u8      pll;
 368         u8      pll_shift;
 369 };
 370
 371 static void pll_init_one(int pll, int m, int n, int od)
 372 {
 373         void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
 374         void __iomem *pll_reg = cpm_regs + CPM_CPAPCR + ((pll - 1) * 4);
 375
 376         setbits_le32(pll_reg, M_N_OD(m, n, od) | XPLLEN);
 377
 378         /* FIXME */
 379         while (!(readl(pll_reg) & XPLL_ON))
 380                 ;
 381 }
 382
 383 static void cpu_mux_select(int pll)
 384 {
 385         void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
 386         u32 clk_ctrl;
 387         unsigned int selectplls[] = {
 388                 CPM_PLL_SEL_STOP,
 389                 CPM_PLL_SEL_SRC,
 390                 CPM_PLL_SEL_MPLL,
 391                 CPM_PLL_SEL_EPLL
 392         };
 393
 394         /* Init CPU, L2CACHE, AHB0, AHB2, APB clock */
 395         clk_ctrl = CPM_CPCCR_CE_CPU | CPM_CPCCR_CE_AHB0 | CPM_CPCCR_CE_AHB2 |
 396                         ((6 - 1) << CPM_CPCCR_H2DIV_BIT) |
 397                         ((3 - 1) << CPM_CPCCR_H0DIV_BIT) |
 398                         ((2 - 1) << CPM_CPCCR_L2DIV_BIT) |
 399                         ((1 - 1) << CPM_CPCCR_CDIV_BIT);
 400
 401         if (CONFIG_SYS_MHZ >= 1000)
 402                 clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
 403         else
 404                 clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT;
 405
 406         clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl);
 407
 408         while (readl(cpm_regs + CPM_CPCSR) & (CPM_CPCSR_CDIV_BUSY |
 409                CPM_CPCSR_H0DIV_BUSY | CPM_CPCSR_H2DIV_BUSY))
 410                 ;
 411
 412         clk_ctrl = (selectplls[pll] << CPM_CPCCR_SEL_CPLL_BIT) |
 413                    (selectplls[MPLL] << CPM_CPCCR_SEL_H0PLL_BIT) |
 414                    (selectplls[MPLL] << CPM_CPCCR_SEL_H2PLL_BIT);
 415         if (pll == APLL)
 416                 clk_ctrl |= CPM_PLL_SEL_SRC << CPM_CPCCR_SEL_SRC_BIT;
 417         else
 418                 clk_ctrl |= CPM_SRC_SEL_EXCLK << CPM_CPCCR_SEL_SRC_BIT;
 419
 420         clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl);
 421 }
 422
 423 static void ddr_mux_select(int pll)
 424 {
 425         void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
 426         int selectplls[] = { CPM_DDRCDR_DCS_STOP,
 427                              CPM_DDRCDR_DCS_SRC,
 428                              CPM_DDRCDR_DCS_MPLL};
 429
 430         writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1),
 431                cpm_regs + CPM_DDCDR);
 432
 433         while (readl(cpm_regs + CPM_DDCDR) & CPM_DDRCDR_DDR_BUSY)
 434                 ;
 435
 436         clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_DDR0);
 437
 438         mdelay(200);
 439 }
 440
 441 static void cgu_mux_init(struct cgu_pll_select *cgu, unsigned int num)
 442 {
 443         void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
 444         unsigned int selectplls[] = {0, 1, 2, 3, 2, 6};
 445         int i;
 446
 447         for (i = 0; i < num; i++)
 448                 writel(selectplls[cgu[i].pll] << cgu[i].pll_shift,
 449                        cpm_regs + cgu[i].reg);
 450 }
 451
 452 void pll_init(void)
 453 {
 454         void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
 455         struct cgu_pll_select cgu_mux[] = {
 456                 { CPM_MSCCDR,  MPLL, 30 },
 457                 { CPM_LPCDR,   VPLL, 30 },
 458                 { CPM_LPCDR1,  VPLL, 30 },
 459                 { CPM_GPUCDR,  MPLL, 30 },
 460                 { CPM_HDMICDR, VPLL, 30 },
 461                 { CPM_I2SCDR,  EPLL, 30 },
 462                 { CPM_BCHCDR,  MPLL, 30 },
 463                 { CPM_VPUCDR,  0x1,  30 },
 464                 { CPM_UHCCDR,  0x3,  30 },
 465                 { CPM_CIMCDR,  0x1,  31 },
 466                 { CPM_PCMCDR,  0x5,  29 },
 467                 { CPM_SSICDR,  0x3,  30 },
 468         };
 469
 470         /* PLL stable time set to default -- 1ms */
 471         clrsetbits_le32(cpm_regs + CPM_CPPCR, 0xfffff, (16 << 8) | 0x20);
 472
 473         pll_init_one(APLL, JZ4780_APLL_M, JZ4780_APLL_N, JZ4780_APLL_OD);
 474         pll_init_one(MPLL, JZ4780_MPLL_M, JZ4780_MPLL_N, JZ4780_MPLL_OD);
 475         pll_init_one(VPLL, JZ4780_VPLL_M, JZ4780_VPLL_N, JZ4780_VPLL_OD);
 476         pll_init_one(EPLL, JZ4780_EPLL_M, JZ4780_EPLL_N, JZ4780_EPLL_OD);
 477
 478         cpu_mux_select(MPLL);
 479         ddr_mux_select(MPLL);
 480         cgu_mux_init(cgu_mux, ARRAY_SIZE(cgu_mux));
 481 }
 482
 483 const u32 jz4780_clk_get_efuse_clk(void)
 484 {
 485         void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
 486         u32 cpccr = readl(cpm_regs + CPM_CPCCR);
 487         u32 ahb2_div = ((cpccr & CPM_CPCCR_H2DIV_MASK) >>
 488                         CPM_CPCCR_H2DIV_BIT) + 1;
 489         return JZ4780_SYS_MEM_SPEED / ahb2_div;
 490 }
 491
 492 void jz4780_clk_ungate_ethernet(void)
 493 {
 494         void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
 495
 496         clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_MAC);
 497         clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_NEMC);
 498 }
 499
 500 void jz4780_clk_ungate_mmc(void)
 501 {
 502         void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
 503         u32 msc_cdr = JZ4780_SYS_MEM_SPEED / 24000000 / 2 - 1;
 504
 505         msc_cdr |= CPM_MSCCDR_MPCS_MPLL | CPM_MSCCDR_CE;
 506         writel(msc_cdr, cpm_regs + CPM_MSCCDR);
 507         writel(msc_cdr, cpm_regs + CPM_MSCCDR1);
 508         writel(msc_cdr, cpm_regs + CPM_MSCCDR2);
 509
 510         /* The wait_for_bit() won't fit, thus unbounded loop here. */
 511         while (readl(cpm_regs + CPM_MSCCDR1) & CPM_MSCCDR_MSC_BUSY)
 512                 ;
 513 }
 514
 515 void jz4780_clk_ungate_uart(const unsigned int uart)
 516 {
 517         void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
 518
 519         if (uart == 0)
 520                 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART0);
 521         else if (uart == 1)
 522                 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART1);
 523         else if (uart == 2)
 524                 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART2);
 525         else if (uart == 3)
 526                 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART3);
 527         else if (uart == 4)
 528                 clrbits_le32(cpm_regs + CPM_CLKGR1, CPM_CLKGR1_UART4);
 529         else
 530                 printf("%s[%i]: Invalid UART %d\n", __func__, __LINE__, uart);
 531 }