arch/mips/mach-ath79/qca953x/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
   4  * Based on Atheros LSDK/QSDK
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/addrspace.h>
  10 #include <asm/types.h>
  11 #include <mach/ar71xx_regs.h>
  12 #include <mach/ath79.h>
  13
  14 #define DDR_CTRL_UPD_EMR3S      BIT(5)
  15 #define DDR_CTRL_UPD_EMR2S      BIT(4)
  16 #define DDR_CTRL_PRECHARGE      BIT(3)
  17 #define DDR_CTRL_AUTO_REFRESH   BIT(2)
  18 #define DDR_CTRL_UPD_EMRS       BIT(1)
  19 #define DDR_CTRL_UPD_MRS        BIT(0)
  20
  21 #define DDR_REFRESH_EN          BIT(14)
  22 #define DDR_REFRESH_M           0x3ff
  23 #define DDR_REFRESH(x)          ((x) & DDR_REFRESH_M)
  24 #define DDR_REFRESH_VAL         (DDR_REFRESH_EN | DDR_REFRESH(312))
  25
  26 #define DDR_TRAS_S              0
  27 #define DDR_TRAS_M              0x1f
  28 #define DDR_TRAS(x)             (((x) & DDR_TRAS_M) << DDR_TRAS_S)
  29 #define DDR_TRCD_M              0xf
  30 #define DDR_TRCD_S              5
  31 #define DDR_TRCD(x)             (((x) & DDR_TRCD_M) << DDR_TRCD_S)
  32 #define DDR_TRP_M               0xf
  33 #define DDR_TRP_S               9
  34 #define DDR_TRP(x)              (((x) & DDR_TRP_M) << DDR_TRP_S)
  35 #define DDR_TRRD_M              0xf
  36 #define DDR_TRRD_S              13
  37 #define DDR_TRRD(x)             (((x) & DDR_TRRD_M) << DDR_TRRD_S)
  38 #define DDR_TRFC_M              0x7f
  39 #define DDR_TRFC_S              17
  40 #define DDR_TRFC(x)             (((x) & DDR_TRFC_M) << DDR_TRFC_S)
  41 #define DDR_TMRD_M              0xf
  42 #define DDR_TMRD_S              23
  43 #define DDR_TMRD(x)             (((x) & DDR_TMRD_M) << DDR_TMRD_S)
  44 #define DDR_CAS_L_M             0x17
  45 #define DDR_CAS_L_S             27
  46 #define DDR_CAS_L(x)            (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
  47 #define DDR_OPEN                BIT(30)
  48 #define DDR1_CONF_REG_VAL       (DDR_TRAS(16) | DDR_TRCD(6) | \
  49                                  DDR_TRP(6) | DDR_TRRD(4) | \
  50                                  DDR_TRFC(7) | DDR_TMRD(5) | \
  51                                  DDR_CAS_L(7) | DDR_OPEN)
  52 #define DDR2_CONF_REG_VAL       (DDR_TRAS(27) | DDR_TRCD(9) | \
  53                                  DDR_TRP(9) | DDR_TRRD(7) | \
  54                                  DDR_TRFC(21) | DDR_TMRD(15) | \
  55                                  DDR_CAS_L(17) | DDR_OPEN)
  56
  57 #define DDR_BURST_LEN_S         0
  58 #define DDR_BURST_LEN_M         0xf
  59 #define DDR_BURST_LEN(x)        ((x) << DDR_BURST_LEN_S)
  60 #define DDR_BURST_TYPE          BIT(4)
  61 #define DDR_CNTL_OE_EN          BIT(5)
  62 #define DDR_PHASE_SEL           BIT(6)
  63 #define DDR_CKE                 BIT(7)
  64 #define DDR_TWR_S               8
  65 #define DDR_TWR_M               0xf
  66 #define DDR_TWR(x)              (((x) & DDR_TWR_M) << DDR_TWR_S)
  67 #define DDR_TRTW_S              12
  68 #define DDR_TRTW_M              0x1f
  69 #define DDR_TRTW(x)             (((x) & DDR_TRTW_M) << DDR_TRTW_S)
  70 #define DDR_TRTP_S              17
  71 #define DDR_TRTP_M              0xf
  72 #define DDR_TRTP(x)             (((x) & DDR_TRTP_M) << DDR_TRTP_S)
  73 #define DDR_TWTR_S              21
  74 #define DDR_TWTR_M              0x1f
  75 #define DDR_TWTR(x)             (((x) & DDR_TWTR_M) << DDR_TWTR_S)
  76 #define DDR_G_OPEN_L_S          26
  77 #define DDR_G_OPEN_L_M          0xf
  78 #define DDR_G_OPEN_L(x)         ((x) << DDR_G_OPEN_L_S)
  79 #define DDR_HALF_WIDTH_LOW      BIT(31)
  80 #define DDR1_CONF2_REG_VAL      (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
  81                                  DDR_CKE | DDR_TWR(13) | DDR_TRTW(14) | \
  82                                  DDR_TRTP(8) | DDR_TWTR(14) | \
  83                                  DDR_G_OPEN_L(6) | DDR_HALF_WIDTH_LOW)
  84 #define DDR2_CONF2_REG_VAL      (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
  85                                  DDR_CKE | DDR_TWR(1) | DDR_TRTW(14) | \
  86                                  DDR_TRTP(9) | DDR_TWTR(21) | \
  87                                  DDR_G_OPEN_L(8) | DDR_HALF_WIDTH_LOW)
  88
  89 #define DDR_TWR_MSB             BIT(3)
  90 #define DDR_TRAS_MSB            BIT(2)
  91 #define DDR_TRFC_MSB_M          0x3
  92 #define DDR_TRFC_MSB(x)         (x)
  93 #define DDR1_CONF3_REG_VAL      0
  94 #define DDR2_CONF3_REG_VAL      (DDR_TWR_MSB | DDR_TRFC_MSB(2))
  95
  96 #define DDR_CTL_SRAM_TSEL       BIT(30)
  97 #define DDR_CTL_SRAM_GE0_SYNC   BIT(20)
  98 #define DDR_CTL_SRAM_GE1_SYNC   BIT(19)
  99 #define DDR_CTL_SRAM_USB_SYNC   BIT(18)
 100 #define DDR_CTL_SRAM_PCIE_SYNC  BIT(17)
 101 #define DDR_CTL_SRAM_WMAC_SYNC  BIT(16)
 102 #define DDR_CTL_SRAM_MISC1_SYNC BIT(15)
 103 #define DDR_CTL_SRAM_MISC2_SYNC BIT(14)
 104 #define DDR_CTL_PAD_DDR2_SEL    BIT(6)
 105 #define DDR_CTL_HALF_WIDTH      BIT(1)
 106 #define DDR_CTL_CONFIG_VAL      (DDR_CTL_SRAM_TSEL | \
 107                                  DDR_CTL_SRAM_GE0_SYNC | \
 108                                  DDR_CTL_SRAM_GE1_SYNC | \
 109                                  DDR_CTL_SRAM_USB_SYNC | \
 110                                  DDR_CTL_SRAM_PCIE_SYNC | \
 111                                  DDR_CTL_SRAM_WMAC_SYNC | \
 112                                  DDR_CTL_HALF_WIDTH)
 113
 114 #define DDR_BURST_GE0_MAX_BL_S  0
 115 #define DDR_BURST_GE0_MAX_BL_M  0xf
 116 #define DDR_BURST_GE0_MAX_BL(x) \
 117         (((x) & DDR_BURST_GE0_MAX_BL_M) << DDR_BURST_GE0_MAX_BL_S)
 118 #define DDR_BURST_GE1_MAX_BL_S  4
 119 #define DDR_BURST_GE1_MAX_BL_M  0xf
 120 #define DDR_BURST_GE1_MAX_BL(x) \
 121         (((x) & DDR_BURST_GE1_MAX_BL_M) << DDR_BURST_GE1_MAX_BL_S)
 122 #define DDR_BURST_PCIE_MAX_BL_S 8
 123 #define DDR_BURST_PCIE_MAX_BL_M 0xf
 124 #define DDR_BURST_PCIE_MAX_BL(x) \
 125         (((x) & DDR_BURST_PCIE_MAX_BL_M) << DDR_BURST_PCIE_MAX_BL_S)
 126 #define DDR_BURST_USB_MAX_BL_S  12
 127 #define DDR_BURST_USB_MAX_BL_M  0xf
 128 #define DDR_BURST_USB_MAX_BL(x) \
 129         (((x) & DDR_BURST_USB_MAX_BL_M) << DDR_BURST_USB_MAX_BL_S)
 130 #define DDR_BURST_CPU_MAX_BL_S  16
 131 #define DDR_BURST_CPU_MAX_BL_M  0xf
 132 #define DDR_BURST_CPU_MAX_BL(x) \
 133         (((x) & DDR_BURST_CPU_MAX_BL_M) << DDR_BURST_CPU_MAX_BL_S)
 134 #define DDR_BURST_RD_MAX_BL_S   20
 135 #define DDR_BURST_RD_MAX_BL_M   0xf
 136 #define DDR_BURST_RD_MAX_BL(x) \
 137         (((x) & DDR_BURST_RD_MAX_BL_M) << DDR_BURST_RD_MAX_BL_S)
 138 #define DDR_BURST_WR_MAX_BL_S   24
 139 #define DDR_BURST_WR_MAX_BL_M   0xf
 140 #define DDR_BURST_WR_MAX_BL(x) \
 141         (((x) & DDR_BURST_WR_MAX_BL_M) << DDR_BURST_WR_MAX_BL_S)
 142 #define DDR_BURST_RWP_MASK_EN_S 28
 143 #define DDR_BURST_RWP_MASK_EN_M 0x3
 144 #define DDR_BURST_RWP_MASK_EN(x) \
 145         (((x) & DDR_BURST_RWP_MASK_EN_M) << DDR_BURST_RWP_MASK_EN_S)
 146 #define DDR_BURST_CPU_PRI_BE    BIT(30)
 147 #define DDR_BURST_CPU_PRI       BIT(31)
 148 #define DDR_BURST_VAL           (DDR_BURST_CPU_PRI_BE | \
 149                                  DDR_BURST_RWP_MASK_EN(3) | \
 150                                  DDR_BURST_WR_MAX_BL(4) | \
 151                                  DDR_BURST_RD_MAX_BL(4) | \
 152                                  DDR_BURST_CPU_MAX_BL(4) | \
 153                                  DDR_BURST_USB_MAX_BL(4) | \
 154                                  DDR_BURST_PCIE_MAX_BL(4) | \
 155                                  DDR_BURST_GE1_MAX_BL(4) | \
 156                                  DDR_BURST_GE0_MAX_BL(4))
 157
 158 #define DDR_BURST_WMAC_MAX_BL_S 0
 159 #define DDR_BURST_WMAC_MAX_BL_M 0xf
 160 #define DDR_BURST_WMAC_MAX_BL(x) \
 161         (((x) & DDR_BURST_WMAC_MAX_BL_M) << DDR_BURST_WMAC_MAX_BL_S)
 162 #define DDR_BURST2_VAL          DDR_BURST_WMAC_MAX_BL(4)
 163
 164 #define DDR2_CONF_TWL_S         10
 165 #define DDR2_CONF_TWL_M         0xf
 166 #define DDR2_CONF_TWL(x) \
 167         (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
 168 #define DDR2_CONF_ODT           BIT(9)
 169 #define DDR2_CONF_TFAW_S        2
 170 #define DDR2_CONF_TFAW_M        0x3f
 171 #define DDR2_CONF_TFAW(x) \
 172         (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
 173 #define DDR2_CONF_EN            BIT(0)
 174 #define DDR2_CONF_VAL           (DDR2_CONF_TWL(5) | \
 175                                  DDR2_CONF_TFAW(31) | \
 176                                  DDR2_CONF_ODT | \
 177                                  DDR2_CONF_EN)
 178
 179 #define DDR1_EXT_MODE_VAL       0
 180 #define DDR2_EXT_MODE_VAL       0x402
 181 #define DDR2_EXT_MODE_OCD_VAL   0x782
 182 #define DDR1_MODE_DLL_VAL       0x133
 183 #define DDR2_MODE_DLL_VAL       0x143
 184 #define DDR1_MODE_VAL           0x33
 185 #define DDR2_MODE_VAL           0x43
 186 #define DDR1_TAP_VAL            0x20
 187 #define DDR2_TAP_VAL            0x10
 188
 189 #define DDR_REG_BIST_MASK_ADDR_0        0x2c
 190 #define DDR_REG_BIST_MASK_ADDR_1        0x30
 191 #define DDR_REG_BIST_MASK_AHB_GE0_0     0x34
 192 #define DDR_REG_BIST_COMP_AHB_GE0_0     0x38
 193 #define DDR_REG_BIST_MASK_AHB_GE1_0     0x3c
 194 #define DDR_REG_BIST_COMP_AHB_GE1_0     0x40
 195 #define DDR_REG_BIST_COMP_ADDR_0        0x64
 196 #define DDR_REG_BIST_COMP_ADDR_1        0x68
 197 #define DDR_REG_BIST_MASK_AHB_GE0_1     0x6c
 198 #define DDR_REG_BIST_COMP_AHB_GE0_1     0x70
 199 #define DDR_REG_BIST_MASK_AHB_GE1_1     0x74
 200 #define DDR_REG_BIST_COMP_AHB_GE1_1     0x78
 201 #define DDR_REG_BIST                    0x11c
 202 #define DDR_REG_BIST_STATUS             0x120
 203
 204 #define DDR_BIST_COMP_CNT_S     1
 205 #define DDR_BIST_COMP_CNT_M     0xff
 206 #define DDR_BIST_COMP_CNT(x) \
 207         (((x) & DDR_BIST_COMP_CNT_M) << DDR_BIST_COMP_CNT_S)
 208 #define DDR_BIST_COMP_CNT_MASK \
 209         (DDR_BIST_COMP_CNT_M << DDR_BIST_COMP_CNT_S)
 210 #define DDR_BIST_TEST_START     BIT(0)
 211 #define DDR_BIST_STATUS_DONE    BIT(0)
 212
 213 /* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */
 214 #define DDR_BIST_MASK_ADDR_VAL  0xfa5de83f
 215
 216 #define DDR_TAP_MAGIC_VAL       0xaa55aa55
 217 #define DDR_TAP_MAX_VAL         0x40
 218
 219 void ddr_init(void)
 220 {
 221         void __iomem *regs;
 222         u32 val;
 223
 224         regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
 225                            MAP_NOCACHE);
 226         val = ath79_get_bootstrap();
 227         if (val & QCA953X_BOOTSTRAP_DDR1) {
 228                 writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
 229                 udelay(10);
 230
 231                 /* For 16-bit DDR */
 232                 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
 233                 udelay(100);
 234
 235                 /* Burst size */
 236                 writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
 237                 udelay(100);
 238                 writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
 239                 udelay(100);
 240
 241                 /* AHB maximum timeout */
 242                 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
 243                 udelay(100);
 244
 245                 /* DRAM timing */
 246                 writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
 247                 udelay(100);
 248                 writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
 249                 udelay(100);
 250                 writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
 251                 udelay(100);
 252
 253                 /* Precharge All */
 254                 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 255                 udelay(100);
 256
 257                 /* ODT disable, Full strength, Enable DLL */
 258                 writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
 259                 udelay(100);
 260
 261                 /* Update Extended Mode Register Set (EMRS) */
 262                 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 263                 udelay(100);
 264
 265                 /* Reset DLL, CAS Latency 3, Burst Length 8 */
 266                 writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
 267                 udelay(100);
 268
 269                 /* Update Mode Register Set (MRS) */
 270                 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 271                 udelay(100);
 272
 273                 /* Precharge All */
 274                 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 275                 udelay(100);
 276
 277                 /* Auto Refresh */
 278                 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
 279                 udelay(100);
 280                 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
 281                 udelay(100);
 282
 283                 /* Normal DLL, CAS Latency 3, Burst Length 8 */
 284                 writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
 285                 udelay(100);
 286
 287                 /* Update Mode Register Set (MRS) */
 288                 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 289                 udelay(100);
 290
 291                 /* Refresh time control */
 292                 writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
 293                 udelay(100);
 294
 295                 /* DQS 0 Tap Control */
 296                 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
 297
 298                 /* DQS 1 Tap Control */
 299                 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
 300         } else {
 301                 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
 302                 udelay(10);
 303                 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
 304                 udelay(10);
 305                 writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL,
 306                        regs + QCA953X_DDR_REG_CTL_CONF);
 307                 udelay(10);
 308
 309                 /* For 16-bit DDR */
 310                 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
 311                 udelay(100);
 312
 313                 /* Burst size */
 314                 writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
 315                 udelay(100);
 316                 writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
 317                 udelay(100);
 318
 319                 /* AHB maximum timeout */
 320                 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
 321                 udelay(100);
 322
 323                 /* DRAM timing */
 324                 writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
 325                 udelay(100);
 326                 writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
 327                 udelay(100);
 328                 writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
 329                 udelay(100);
 330
 331                 /* Enable DDR2 */
 332                 writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG);
 333                 udelay(100);
 334
 335                 /* Precharge All */
 336                 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 337                 udelay(100);
 338
 339                 /* Update Extended Mode Register 2 Set (EMR2S) */
 340                 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
 341                 udelay(100);
 342
 343                 /* Update Extended Mode Register 3 Set (EMR3S) */
 344                 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
 345                 udelay(100);
 346
 347                 /* 150 ohm, Reduced strength, Enable DLL */
 348                 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
 349                 udelay(100);
 350
 351                 /* Update Extended Mode Register Set (EMRS) */
 352                 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 353                 udelay(100);
 354
 355                 /* Reset DLL, CAS Latency 4, Burst Length 8 */
 356                 writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
 357                 udelay(100);
 358
 359                 /* Update Mode Register Set (MRS) */
 360                 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 361                 udelay(100);
 362
 363                 /* Precharge All */
 364                 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 365                 udelay(100);
 366
 367                 /* Auto Refresh */
 368                 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
 369                 udelay(100);
 370                 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
 371                 udelay(100);
 372
 373                 /* Normal DLL, CAS Latency 4, Burst Length 8 */
 374                 writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
 375                 udelay(100);
 376
 377                 /* Mode Register Set (MRS) */
 378                 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 379                 udelay(100);
 380
 381                 /* Enable OCD, Enable DLL, Reduced Drive Strength */
 382                 writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
 383                 udelay(100);
 384
 385                 /* Update Extended Mode Register Set (EMRS) */
 386                 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 387                 udelay(100);
 388
 389                 /* OCD diable, Enable DLL, Reduced Drive Strength */
 390                 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
 391                 udelay(100);
 392
 393                 /* Update Extended Mode Register Set (EMRS) */
 394                 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 395                 udelay(100);
 396
 397                 /* Refresh time control */
 398                 writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
 399                 udelay(100);
 400
 401                 /* DQS 0 Tap Control */
 402                 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
 403
 404                 /* DQS 1 Tap Control */
 405                 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
 406         }
 407 }
 408
 409 void ddr_tap_tuning(void)
 410 {
 411         void __iomem *regs;
 412         u32 val, pass, tap, cnt, tap_val, last, first;
 413
 414         regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
 415                            MAP_NOCACHE);
 416
 417         tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
 418         first = DDR_TAP_MAGIC_VAL;
 419         last = 0;
 420         cnt = 0;
 421         tap = 0;
 422
 423         do {
 424                 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0);
 425                 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1);
 426
 427                 writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1);
 428                 writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0);
 429                 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1);
 430                 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0);
 431                 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1);
 432                 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0);
 433                 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1);
 434                 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0);
 435                 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1);
 436                 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0);
 437
 438                 /* Start BIST test */
 439                 writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST);
 440
 441                 do {
 442                         val = readl(regs + DDR_REG_BIST_STATUS);
 443                 } while (!(val & DDR_BIST_STATUS_DONE));
 444
 445                 /* Stop BIST test */
 446                 writel(0, regs + DDR_REG_BIST);
 447
 448                 pass = val & DDR_BIST_COMP_CNT_MASK;
 449                 pass ^= DDR_BIST_COMP_CNT(8);
 450                 if (!pass) {
 451                         if (first != DDR_TAP_MAGIC_VAL) {
 452                                 last = tap;
 453                         } else  {
 454                                 first = tap;
 455                                 last = tap;
 456                         }
 457                         cnt++;
 458                 }
 459                 tap++;
 460         } while (tap < DDR_TAP_MAX_VAL);
 461
 462         if (cnt) {
 463                 tap_val = (first + last) / 2;
 464                 tap_val %= DDR_TAP_MAX_VAL;
 465         }
 466
 467         writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0);
 468         writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1);
 469 }