arch/mips/mach-ath79/ar933x/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
   4  * Based on Atheros LSDK/QSDK
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/addrspace.h>
  10 #include <asm/types.h>
  11 #include <linux/bitops.h>
  12 #include <mach/ar71xx_regs.h>
  13 #include <mach/ath79.h>
  14
  15 #define DDR_CTRL_UPD_EMR3S      BIT(5)
  16 #define DDR_CTRL_UPD_EMR2S      BIT(4)
  17 #define DDR_CTRL_PRECHARGE      BIT(3)
  18 #define DDR_CTRL_AUTO_REFRESH   BIT(2)
  19 #define DDR_CTRL_UPD_EMRS       BIT(1)
  20 #define DDR_CTRL_UPD_MRS        BIT(0)
  21
  22 #define DDR_REFRESH_EN          BIT(14)
  23 #define DDR_REFRESH_M           0x3ff
  24 #define DDR_REFRESH(x)          ((x) & 0x3ff)
  25 #define DDR_REFRESH_VAL_25M     (DDR_REFRESH_EN | DDR_REFRESH(390))
  26 #define DDR_REFRESH_VAL_40M     (DDR_REFRESH_EN | DDR_REFRESH(624))
  27
  28 #define DDR_TRAS_S              0
  29 #define DDR_TRAS_M              0x1f
  30 #define DDR_TRAS(x)             ((x) << DDR_TRAS_S)
  31 #define DDR_TRCD_M              0xf
  32 #define DDR_TRCD_S              5
  33 #define DDR_TRCD(x)             ((x) << DDR_TRCD_S)
  34 #define DDR_TRP_M               0xf
  35 #define DDR_TRP_S               9
  36 #define DDR_TRP(x)              ((x) << DDR_TRP_S)
  37 #define DDR_TRRD_M              0xf
  38 #define DDR_TRRD_S              13
  39 #define DDR_TRRD(x)             ((x) << DDR_TRRD_S)
  40 #define DDR_TRFC_M              0x7f
  41 #define DDR_TRFC_S              17
  42 #define DDR_TRFC(x)             ((x) << DDR_TRFC_S)
  43 #define DDR_TMRD_M              0xf
  44 #define DDR_TMRD_S              23
  45 #define DDR_TMRD(x)             ((x) << DDR_TMRD_S)
  46 #define DDR_CAS_L_M             0x17
  47 #define DDR_CAS_L_S             27
  48 #define DDR_CAS_L(x)            (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
  49 #define DDR_OPEN                BIT(30)
  50 #define DDR_CONF_REG_VAL        (DDR_TRAS(16) | DDR_TRCD(6) | \
  51                                  DDR_TRP(6) | DDR_TRRD(4) | \
  52                                  DDR_TRFC(30) | DDR_TMRD(15) | \
  53                                  DDR_CAS_L(7) | DDR_OPEN)
  54
  55 #define DDR_BURST_LEN_S         0
  56 #define DDR_BURST_LEN_M         0xf
  57 #define DDR_BURST_LEN(x)        ((x) << DDR_BURST_LEN_S)
  58 #define DDR_BURST_TYPE          BIT(4)
  59 #define DDR_CNTL_OE_EN          BIT(5)
  60 #define DDR_PHASE_SEL           BIT(6)
  61 #define DDR_CKE                 BIT(7)
  62 #define DDR_TWR_S               8
  63 #define DDR_TWR_M               0xf
  64 #define DDR_TWR(x)              ((x) << DDR_TWR_S)
  65 #define DDR_TRTW_S              12
  66 #define DDR_TRTW_M              0x1f
  67 #define DDR_TRTW(x)             ((x) << DDR_TRTW_S)
  68 #define DDR_TRTP_S              17
  69 #define DDR_TRTP_M              0xf
  70 #define DDR_TRTP(x)             ((x) << DDR_TRTP_S)
  71 #define DDR_TWTR_S              21
  72 #define DDR_TWTR_M              0x1f
  73 #define DDR_TWTR(x)             ((x) << DDR_TWTR_S)
  74 #define DDR_G_OPEN_L_S          26
  75 #define DDR_G_OPEN_L_M          0xf
  76 #define DDR_G_OPEN_L(x)         ((x) << DDR_G_OPEN_L_S)
  77 #define DDR_HALF_WIDTH_LOW      BIT(31)
  78 #define DDR_CONF2_REG_VAL       (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
  79                                  DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
  80                                  DDR_TRTP(8) | DDR_TWTR(14) | \
  81                                  DDR_G_OPEN_L(7) | DDR_HALF_WIDTH_LOW)
  82
  83 #define DDR2_CONF_TWL_S         10
  84 #define DDR2_CONF_TWL_M         0xf
  85 #define DDR2_CONF_TWL(x)        (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
  86 #define DDR2_CONF_ODT           BIT(9)
  87 #define DDR2_CONF_TFAW_S        2
  88 #define DDR2_CONF_TFAW_M        0x3f
  89 #define DDR2_CONF_TFAW(x)       (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
  90 #define DDR2_CONF_EN            BIT(0)
  91 #define DDR2_CONF_VAL           (DDR2_CONF_TWL(2) | DDR2_CONF_ODT | \
  92                                  DDR2_CONF_TFAW(22) | DDR2_CONF_EN)
  93
  94 #define DDR1_EXT_MODE_VAL       0x02
  95 #define DDR2_EXT_MODE_VAL       0x402
  96 #define DDR2_EXT_MODE_OCD_VAL   0x382
  97 #define DDR1_MODE_DLL_VAL       0x133
  98 #define DDR2_MODE_DLL_VAL       0x100
  99 #define DDR1_MODE_VAL           0x33
 100 #define DDR2_MODE_VAL           0xa33
 101 #define DDR_TAP_VAL0            0x08
 102 #define DDR_TAP_VAL1            0x09
 103
 104 void ddr_init(void)
 105 {
 106         void __iomem *regs;
 107         u32 val;
 108
 109         regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
 110                            MAP_NOCACHE);
 111
 112         writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
 113         writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
 114
 115         val = ath79_get_bootstrap();
 116         if (val & AR933X_BOOTSTRAP_DDR2) {
 117                 /* AHB maximum timeout */
 118                 writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
 119
 120                 /* Enable DDR2 */
 121                 writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
 122
 123                 /* Precharge All */
 124                 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 125
 126                 /* Disable High Temperature Self-Refresh, Full Array */
 127                 writel(0x00, regs + AR933X_DDR_REG_EMR2);
 128
 129                 /* Extended Mode Register 2 Set (EMR2S) */
 130                 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
 131
 132                 writel(0x00, regs + AR933X_DDR_REG_EMR3);
 133
 134                 /* Extended Mode Register 3 Set (EMR3S) */
 135                 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
 136
 137                 /* Enable DLL,  Full strength, ODT Disabled */
 138                 writel(0x00, regs + AR71XX_DDR_REG_EMR);
 139
 140                 /* Extended Mode Register Set (EMRS) */
 141                 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 142
 143                 /* Reset DLL */
 144                 writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
 145
 146                 /* Mode Register Set (MRS) */
 147                 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 148
 149                 /* Precharge All */
 150                 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 151
 152                 /* Auto Refresh */
 153                 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
 154                 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
 155
 156                 /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
 157                 writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
 158                 /* Mode Register Set (MRS) */
 159                 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 160
 161                 /* Enable OCD defaults, Enable DLL, Reduced Drive Strength */
 162                 writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
 163
 164                 /* Extended Mode Register Set (EMRS) */
 165                 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 166
 167                 /* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */
 168                 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
 169                 /* Extended Mode Register Set (EMRS) */
 170                 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 171
 172                 /* Refresh time control */
 173                 if (val & AR933X_BOOTSTRAP_REF_CLK_40)
 174                         writel(DDR_REFRESH_VAL_40M, regs +
 175                                AR71XX_DDR_REG_REFRESH);
 176                 else
 177                         writel(DDR_REFRESH_VAL_25M, regs +
 178                                AR71XX_DDR_REG_REFRESH);
 179
 180                 /* DQS 0 Tap Control */
 181                 writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
 182
 183                 /* DQS 1 Tap Control */
 184                 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
 185
 186                 /* For 16-bit DDR */
 187                 writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
 188         } else {
 189                 /* AHB maximum timeout */
 190                 writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
 191
 192                 /* Precharge All */
 193                 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 194
 195                 /* Reset DLL, Burst Length 8, CAS Latency 3 */
 196                 writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
 197
 198                 /* Forces an MRS update cycle in DDR */
 199                 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 200
 201                 /* Enable DLL, Full strength */
 202                 writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
 203
 204                 /* Extended Mode Register Set (EMRS) */
 205                 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
 206
 207                 /* Precharge All */
 208                 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
 209
 210                 /* Normal DLL, Burst Length 8, CAS Latency 3 */
 211                 writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
 212
 213                 /* Mode Register Set (MRS) */
 214                 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
 215
 216                 /* Refresh time control */
 217                 if (val & AR933X_BOOTSTRAP_REF_CLK_40)
 218                         writel(DDR_REFRESH_VAL_40M, regs +
 219                                AR71XX_DDR_REG_REFRESH);
 220                 else
 221                         writel(DDR_REFRESH_VAL_25M, regs +
 222                                AR71XX_DDR_REG_REFRESH);
 223
 224                 /* DQS 0 Tap Control */
 225                 writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
 226
 227                 /* DQS 1 Tap Control */
 228                 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
 229
 230                 /* For 16-bit DDR */
 231                 writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
 232         }
 233 }
 234
 235 void ddr_tap_tuning(void)
 236 {
 237         void __iomem *regs;
 238         u32 *addr_k0, *addr_k1, *addr;
 239         u32 val, tap, upper, lower;
 240         int i, j, dir, err, done;
 241
 242         regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
 243                            MAP_NOCACHE);
 244
 245         /* Init memory pattern */
 246         addr = (void *)CKSEG0ADDR(0x2000);
 247         for (i = 0; i < 256; i++) {
 248                 val = 0;
 249                 for (j = 0; j < 8; j++) {
 250                         if (i & (1 << j)) {
 251                                 if (j % 2)
 252                                         val |= 0xffff0000;
 253                                 else
 254                                         val |= 0x0000ffff;
 255                         }
 256
 257                         if (j % 2) {
 258                                 *addr++ = val;
 259                                 val = 0;
 260                         }
 261                 }
 262         }
 263
 264         err = 0;
 265         done = 0;
 266         dir = 1;
 267         tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
 268         val = tap;
 269         upper = tap;
 270         lower = tap;
 271         while (!done) {
 272                 err = 0;
 273
 274                 /* Update new DDR tap value */
 275                 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
 276                 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
 277
 278                 /* Compare DDR with cache */
 279                 for (i = 0; i < 2; i++) {
 280                         addr_k1 = (void *)CKSEG1ADDR(0x2000);
 281                         addr_k0 = (void *)CKSEG0ADDR(0x2000);
 282                         addr = (void *)CKSEG0ADDR(0x3000);
 283
 284                         while (addr_k0 < addr) {
 285                                 if (*addr_k1++ != *addr_k0++) {
 286                                         err = 1;
 287                                         break;
 288                                 }
 289                         }
 290
 291                         if (err)
 292                                 break;
 293                 }
 294
 295                 if (err) {
 296                         /* Save upper/lower threshold if error  */
 297                         if (dir) {
 298                                 dir = 0;
 299                                 val--;
 300                                 upper = val;
 301                                 val = tap;
 302                         } else {
 303                                 val++;
 304                                 lower = val;
 305                                 done = 1;
 306                         }
 307                 } else {
 308                         /* Try the next value until limitation */
 309                         if (dir) {
 310                                 if (val < 0x20) {
 311                                         val++;
 312                                 } else {
 313                                         dir = 0;
 314                                         upper = val;
 315                                         val = tap;
 316                                 }
 317                         } else {
 318                                 if (!val) {
 319                                         lower = val;
 320                                         done = 1;
 321                                 } else {
 322                                         val--;
 323                                 }
 324                         }
 325                 }
 326         }
 327
 328         /* compute an intermediate value and write back */
 329         val = (upper + lower) / 2;
 330         writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
 331         val++;
 332         writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
 333 }