arch/mips/dts/mt7628a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/mt7628-clk.h>
   3 #include <dt-bindings/reset/mt7628-reset.h>
   4
   5 / {
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         compatible = "ralink,mt7628a-soc";
   9
  10         cpus {
  11                 #address-cells = <1>;
  12                 #size-cells = <0>;
  13
  14                 cpu@0 {
  15                         compatible = "mti,mips24KEc";
  16                         device_type = "cpu";
  17                         reg = <0>;
  18                 };
  19         };
  20
  21         cpuintc: interrupt-controller {
  22                 #address-cells = <0>;
  23                 #interrupt-cells = <1>;
  24                 interrupt-controller;
  25                 compatible = "mti,cpu-interrupt-controller";
  26         };
  27
  28         clk48m: clk48m@0 {
  29                 compatible = "fixed-clock";
  30
  31                 clock-frequency = <48000000>;
  32
  33                 #clock-cells = <0>;
  34         };
  35
  36         palmbus@10000000 {
  37                 compatible = "palmbus", "simple-bus";
  38                 reg = <0x10000000 0x200000>;
  39                 ranges = <0x0 0x10000000 0x1FFFFF>;
  40
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43
  44                 sysc: system-controller@0 {
  45                         compatible = "ralink,mt7620a-sysc", "syscon";
  46                         reg = <0x0 0x100>;
  47                 };
  48
  49                 syscon-reboot {
  50                         compatible = "syscon-reboot";
  51                         regmap = <&sysc>;
  52                         offset = <0x34>;
  53                         mask = <0x1>;
  54                 };
  55
  56                 clkctrl: clkctrl@0x2c {
  57                         reg = <0x2c 0x8>, <0x10 0x4>;
  58                         reg-names = "syscfg0", "clkcfg";
  59                         compatible = "mediatek,mt7628-clk";
  60                         #clock-cells = <1>;
  61                         u-boot,dm-pre-reloc;
  62                 };
  63
  64                 rstctrl: rstctrl@0x34 {
  65                         reg = <0x34 0x4>;
  66                         compatible = "mediatek,mtmips-reset";
  67                         #reset-cells = <1>;
  68                 };
  69
  70                 pinctrl: pinctrl@60 {
  71                         compatible = "mediatek,mt7628-pinctrl";
  72                         reg = <0x3c 0x2c>, <0x1300 0x100>;
  73                         reg-names = "gpiomode", "padconf";
  74
  75                         pinctrl-names = "default";
  76                         pinctrl-0 = <&state_default>;
  77
  78                         state_default: pin_state {
  79                         };
  80
  81                         spi_single_pins: spi_single_pins {
  82                                 groups = "spi";
  83                                 function = "spi";
  84                         };
  85
  86                         spi_dual_pins: spi_dual_pins {
  87                                 spi_master_pins {
  88                                         groups = "spi";
  89                                         function = "spi";
  90                                 };
  91
  92                                 spi_cs1_pin {
  93                                         groups = "spi cs1";
  94                                         function = "spi cs1";
  95                                 };
  96                         };
  97
  98                         uart0_pins: uart0_pins {
  99                                 groups = "uart0";
 100                                 function = "uart0";
 101                         };
 102
 103                         uart1_pins: uart1_pins {
 104                                 groups = "uart1";
 105                                 function = "uart1";
 106                         };
 107
 108                         uart2_pins: uart2_pins {
 109                                 groups = "uart2";
 110                                 function = "uart2";
 111                         };
 112
 113                         i2c_pins: i2c_pins {
 114                                 groups = "i2c";
 115                                 function = "i2c";
 116                         };
 117
 118                         ephy_iot_mode: ephy_iot_mode {
 119                                 ephy4_1_dis {
 120                                         groups = "ephy4_1_pad";
 121                                         function = "digital";
 122                                 };
 123
 124                                 ephy0_en {
 125                                         groups = "ephy0";
 126                                         function = "enable";
 127                                 };
 128                         };
 129
 130                         ephy_router_mode: ephy_router_mode {
 131                                 ephy4_1_en {
 132                                         groups = "ephy4_1_pad";
 133                                         function = "analog";
 134                                 };
 135
 136                                 ephy0_en {
 137                                         groups = "ephy0";
 138                                         function = "enable";
 139                                 };
 140                         };
 141
 142                         sd_iot_mode: sd_iot_mode {
 143                                 ephy4_1_dis {
 144                                         groups = "ephy4_1_pad";
 145                                         function = "digital";
 146                                 };
 147
 148                                 sdxc_en {
 149                                         groups = "sdmode";
 150                                         function = "sdxc";
 151                                 };
 152
 153                                 sdxc_iot_mode {
 154                                         groups = "sd router";
 155                                         function = "iot";
 156                                 };
 157
 158                                 sd_clk_pad {
 159                                         pins = "sd_clk";
 160                                         drive-strength-4g = <8>;
 161                                 };
 162                         };
 163
 164                         sd_router_mode: sd_router_mode {
 165                                 sdxc_router_mode {
 166                                         groups = "sd router";
 167                                         function = "router";
 168                                 };
 169
 170                                 sdxc_map_pins {
 171                                         groups = "gpio0", "i2s", "sdmode", \
 172                                                  "i2c", "uart1";
 173                                         function = "gpio";
 174                                 };
 175
 176                                 sd_clk_pad {
 177                                         pins = "gpio0";
 178                                         drive-strength-28 = <8>;
 179                                 };
 180                         };
 181
 182                         emmc_iot_8bit_mode: emmc_iot_8bit_mode {
 183                                 ephy4_1_dis {
 184                                         groups = "ephy4_1_pad";
 185                                         function = "digital";
 186                                 };
 187
 188                                 emmc_en {
 189                                         groups = "sdmode";
 190                                         function = "sdxc";
 191                                 };
 192
 193                                 emmc_iot_mode {
 194                                         groups = "sd router";
 195                                         function = "iot";
 196                                 };
 197
 198                                 emmc_d4_d5 {
 199                                         groups = "uart2";
 200                                         function = "sdxc d5 d4";
 201                                 };
 202
 203                                 emmc_d6 {
 204                                         groups = "pwm1";
 205                                         function = "sdxc d6";
 206                                 };
 207
 208                                 emmc_d7 {
 209                                         groups = "pwm0";
 210                                         function = "sdxc d7";
 211                                 };
 212
 213                                 sd_clk_pad {
 214                                         pins = "sd_clk";
 215                                         drive-strength-4g = <8>;
 216                                 };
 217                         };
 218                 };
 219
 220                 watchdog: watchdog@100 {
 221                         compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
 222                         reg = <0x100 0x30>;
 223
 224                         resets = <&rstctrl MT7628_TIMER_RST>;
 225                         reset-names = "wdt";
 226
 227                         interrupt-parent = <&intc>;
 228                         interrupts = <24>;
 229                 };
 230
 231                 intc: interrupt-controller@200 {
 232                         compatible = "ralink,rt2880-intc";
 233                         reg = <0x200 0x100>;
 234
 235                         interrupt-controller;
 236                         #interrupt-cells = <1>;
 237
 238                         resets = <&rstctrl MT7628_INT_RST>;
 239                         reset-names = "intc";
 240
 241                         interrupt-parent = <&cpuintc>;
 242                         interrupts = <2>;
 243
 244                         ralink,intc-registers = <0x9c 0xa0
 245                                                  0x6c 0xa4
 246                                                  0x80 0x78>;
 247                 };
 248
 249                 memory-controller@300 {
 250                         compatible = "ralink,mt7620a-memc";
 251                         reg = <0x300 0x100>;
 252                 };
 253
 254                 gpio@600 {
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257
 258                         compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
 259                         reg = <0x600 0x100>;
 260
 261                         resets = <&rstctrl MT7628_PIO_RST>;
 262                         reset-names = "pio";
 263
 264                         interrupt-parent = <&intc>;
 265                         interrupts = <6>;
 266
 267                         gpio0: bank@0 {
 268                                 reg = <0>;
 269                                 compatible = "mtk,mt7621-gpio-bank";
 270                                 gpio-controller;
 271                                 #gpio-cells = <2>;
 272                         };
 273
 274                         gpio1: bank@1 {
 275                                 reg = <1>;
 276                                 compatible = "mtk,mt7621-gpio-bank";
 277                                 gpio-controller;
 278                                 #gpio-cells = <2>;
 279                         };
 280
 281                         gpio2: bank@2 {
 282                                 reg = <2>;
 283                                 compatible = "mtk,mt7621-gpio-bank";
 284                                 gpio-controller;
 285                                 #gpio-cells = <2>;
 286                         };
 287                 };
 288
 289                 spi0: spi@b00 {
 290                         compatible = "ralink,mt7621-spi";
 291                         reg = <0xb00 0x40>;
 292
 293                         resets = <&rstctrl MT7628_SPI_RST>;
 294                         reset-names = "spi";
 295
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298
 299                         clocks = <&clkctrl CLK_SPI>;
 300                 };
 301
 302                 uart0: uartlite@c00 {
 303                         compatible = "mediatek,hsuart", "ns16550a";
 304                         reg = <0xc00 0x100>;
 305
 306                         pinctrl-names = "default";
 307                         pinctrl-0 = <&uart0_pins>;
 308
 309                         clocks = <&clkctrl CLK_UART0>;
 310
 311                         resets = <&rstctrl MT7628_UART0_RST>;
 312                         reset-names = "uart0";
 313
 314                         interrupt-parent = <&intc>;
 315                         interrupts = <20>;
 316
 317                         reg-shift = <2>;
 318                 };
 319
 320                 uart1: uart1@d00 {
 321                         compatible = "mediatek,hsuart", "ns16550a";
 322                         reg = <0xd00 0x100>;
 323
 324                         pinctrl-names = "default";
 325                         pinctrl-0 = <&uart1_pins>;
 326
 327                         clocks = <&clkctrl CLK_UART1>;
 328
 329                         resets = <&rstctrl MT7628_UART1_RST>;
 330                         reset-names = "uart1";
 331
 332                         interrupt-parent = <&intc>;
 333                         interrupts = <21>;
 334
 335                         reg-shift = <2>;
 336                 };
 337
 338                 uart2: uart2@e00 {
 339                         compatible = "mediatek,hsuart", "ns16550a";
 340                         reg = <0xe00 0x100>;
 341
 342                         pinctrl-names = "default";
 343                         pinctrl-0 = <&uart2_pins>;
 344
 345                         clocks = <&clkctrl CLK_UART2>;
 346
 347                         resets = <&rstctrl MT7628_UART2_RST>;
 348                         reset-names = "uart2";
 349
 350                         interrupt-parent = <&intc>;
 351                         interrupts = <22>;
 352
 353                         reg-shift = <2>;
 354                 };
 355         };
 356
 357         eth: eth@10110000 {
 358                 compatible = "mediatek,mt7628-eth";
 359                 reg = <0x10100000 0x10000
 360                        0x10110000 0x8000>;
 361
 362                 resets = <&rstctrl MT7628_EPHY_RST>;
 363                 reset-names = "ephy";
 364
 365                 syscon = <&sysc>;
 366         };
 367
 368         usb_phy: usb-phy@10120000 {
 369                 compatible = "mediatek,mt7628-usbphy";
 370                 reg = <0x10120000 0x1000>;
 371
 372                 #phy-cells = <0>;
 373
 374                 ralink,sysctl = <&sysc>;
 375
 376                 resets = <&rstctrl MT7628_UPHY_RST>;
 377                 reset-names = "phy";
 378
 379                 clocks = <&clkctrl CLK_UPHY>;
 380                 clock-names = "cg";
 381         };
 382
 383         ehci@101c0000 {
 384                 compatible = "generic-ehci";
 385                 reg = <0x101c0000 0x1000>;
 386
 387                 phys = <&usb_phy>;
 388                 phy-names = "usb";
 389
 390                 interrupt-parent = <&intc>;
 391                 interrupts = <18>;
 392         };
 393
 394         mmc: mmc@10130000 {
 395                 compatible = "mediatek,mt7620-mmc";
 396                 reg = <0x10130000 0x4000>;
 397                 builtin-cd = <1>;
 398                 r_smpl = <1>;
 399
 400                 clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
 401                 clock-names = "source", "hclk";
 402
 403                 resets = <&rstctrl MT7628_SDXC_RST>;
 404
 405                 status = "disabled";
 406         };
 407 };