1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/mt7628-clk.h>
3 #include <dt-bindings/reset/mt7628-reset.h>
8 compatible = "ralink,mt7628a-soc";
15 compatible = "mti,mips24KEc";
21 cpuintc: interrupt-controller {
23 #interrupt-cells = <1>;
25 compatible = "mti,cpu-interrupt-controller";
29 compatible = "fixed-clock";
31 clock-frequency = <48000000>;
36 palmbus: palmbus@10000000 {
37 compatible = "palmbus", "simple-bus";
38 reg = <0x10000000 0x200000>;
39 ranges = <0x0 0x10000000 0x1FFFFF>;
44 sysc: system-controller@0 {
45 compatible = "ralink,mt7620a-sysc", "syscon";
49 reboot: resetctl-reboot {
50 compatible = "resetctl-reboot";
52 resets = <&rstctrl MT7628_SYS_RST>;
53 reset-names = "sysreset";
56 clkctrl: clkctrl@0x2c {
57 reg = <0x2c 0x8>, <0x10 0x4>;
58 reg-names = "syscfg0", "clkcfg";
59 compatible = "mediatek,mt7628-clk";
64 rstctrl: rstctrl@0x34 {
66 compatible = "mediatek,mtmips-reset";
71 compatible = "mediatek,mt7628-pinctrl";
72 reg = <0x3c 0x2c>, <0x1300 0x100>;
73 reg-names = "gpiomode", "padconf";
75 pinctrl-names = "default";
76 pinctrl-0 = <&state_default>;
78 state_default: pin_state {
81 spi_single_pins: spi_single_pins {
86 spi_dual_pins: spi_dual_pins {
98 uart0_pins: uart0_pins {
103 uart1_pins: uart1_pins {
108 uart2_pins: uart2_pins {
113 uart2_pwm_pins: uart2_pwm_pins {
115 function = "pwm_uart2";
123 ephy_iot_mode: ephy_iot_mode {
125 groups = "ephy4_1_pad";
126 function = "digital";
135 ephy_router_mode: ephy_router_mode {
137 groups = "ephy4_1_pad";
147 sd_iot_mode: sd_iot_mode {
149 groups = "ephy4_1_pad";
150 function = "digital";
159 groups = "sd router";
165 drive-strength-4g = <8>;
169 sd_router_mode: sd_router_mode {
171 groups = "sd router";
176 groups = "gpio0", "i2s", "sdmode", \
183 drive-strength-28 = <8>;
187 emmc_iot_8bit_mode: emmc_iot_8bit_mode {
189 groups = "ephy4_1_pad";
190 function = "digital";
199 groups = "sd router";
205 function = "sdxc d5 d4";
210 function = "sdxc d6";
215 function = "sdxc d7";
220 drive-strength-4g = <8>;
225 watchdog: watchdog@100 {
226 compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
229 resets = <&rstctrl MT7628_TIMER_RST>;
232 interrupt-parent = <&intc>;
236 intc: interrupt-controller@200 {
237 compatible = "ralink,rt2880-intc";
240 interrupt-controller;
241 #interrupt-cells = <1>;
243 resets = <&rstctrl MT7628_INT_RST>;
244 reset-names = "intc";
246 interrupt-parent = <&cpuintc>;
249 ralink,intc-registers = <0x9c 0xa0
254 memory-controller@300 {
255 compatible = "ralink,mt7620a-memc";
260 #address-cells = <1>;
263 compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
266 resets = <&rstctrl MT7628_PIO_RST>;
269 interrupt-parent = <&intc>;
274 compatible = "mtk,mt7621-gpio-bank";
281 compatible = "mtk,mt7621-gpio-bank";
288 compatible = "mtk,mt7621-gpio-bank";
295 compatible = "ralink,mt7621-spi";
298 resets = <&rstctrl MT7628_SPI_RST>;
301 #address-cells = <1>;
304 clocks = <&clkctrl CLK_SPI>;
307 uart0: uartlite@c00 {
308 compatible = "mediatek,hsuart", "ns16550a";
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart0_pins>;
314 clocks = <&clkctrl CLK_UART0>;
316 resets = <&rstctrl MT7628_UART0_RST>;
317 reset-names = "uart0";
319 interrupt-parent = <&intc>;
326 compatible = "mediatek,hsuart", "ns16550a";
329 pinctrl-names = "default";
330 pinctrl-0 = <&uart1_pins>;
332 clocks = <&clkctrl CLK_UART1>;
334 resets = <&rstctrl MT7628_UART1_RST>;
335 reset-names = "uart1";
337 interrupt-parent = <&intc>;
344 compatible = "mediatek,hsuart", "ns16550a";
347 pinctrl-names = "default";
348 pinctrl-0 = <&uart2_pins>;
350 clocks = <&clkctrl CLK_UART2>;
352 resets = <&rstctrl MT7628_UART2_RST>;
353 reset-names = "uart2";
355 interrupt-parent = <&intc>;
363 compatible = "mediatek,mt7628-eth";
364 reg = <0x10100000 0x10000
367 resets = <&rstctrl MT7628_EPHY_RST>;
368 reset-names = "ephy";
373 usb_phy: usb-phy@10120000 {
374 compatible = "mediatek,mt7628-usbphy";
375 reg = <0x10120000 0x1000>;
379 ralink,sysctl = <&sysc>;
381 resets = <&rstctrl MT7628_UPHY_RST>;
384 clocks = <&clkctrl CLK_UPHY>;
389 compatible = "generic-ehci";
390 reg = <0x101c0000 0x1000>;
395 interrupt-parent = <&intc>;
400 compatible = "mediatek,mt7620-mmc";
401 reg = <0x10130000 0x4000>;
405 clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
406 clock-names = "source", "hclk";
408 resets = <&rstctrl MT7628_SDXC_RST>;