1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/mt7628-clk.h>
3 #include <dt-bindings/reset/mt7628-reset.h>
8 compatible = "ralink,mt7628a-soc";
15 compatible = "mti,mips24KEc";
21 cpuintc: interrupt-controller {
23 #interrupt-cells = <1>;
25 compatible = "mti,cpu-interrupt-controller";
29 compatible = "fixed-clock";
31 clock-frequency = <48000000>;
37 compatible = "palmbus", "simple-bus";
38 reg = <0x10000000 0x200000>;
39 ranges = <0x0 0x10000000 0x1FFFFF>;
44 sysc: system-controller@0 {
45 compatible = "ralink,mt7620a-sysc", "syscon";
49 reboot: resetctl-reboot {
50 compatible = "resetctl-reboot";
52 resets = <&rstctrl MT7628_SYS_RST>;
53 reset-names = "sysreset";
56 clkctrl: clkctrl@0x2c {
57 reg = <0x2c 0x8>, <0x10 0x4>;
58 reg-names = "syscfg0", "clkcfg";
59 compatible = "mediatek,mt7628-clk";
64 rstctrl: rstctrl@0x34 {
66 compatible = "mediatek,mtmips-reset";
71 compatible = "mediatek,mt7628-pinctrl";
72 reg = <0x3c 0x2c>, <0x1300 0x100>;
73 reg-names = "gpiomode", "padconf";
75 pinctrl-names = "default";
76 pinctrl-0 = <&state_default>;
78 state_default: pin_state {
81 spi_single_pins: spi_single_pins {
86 spi_dual_pins: spi_dual_pins {
98 uart0_pins: uart0_pins {
103 uart1_pins: uart1_pins {
108 uart2_pins: uart2_pins {
118 ephy_iot_mode: ephy_iot_mode {
120 groups = "ephy4_1_pad";
121 function = "digital";
130 ephy_router_mode: ephy_router_mode {
132 groups = "ephy4_1_pad";
142 sd_iot_mode: sd_iot_mode {
144 groups = "ephy4_1_pad";
145 function = "digital";
154 groups = "sd router";
160 drive-strength-4g = <8>;
164 sd_router_mode: sd_router_mode {
166 groups = "sd router";
171 groups = "gpio0", "i2s", "sdmode", \
178 drive-strength-28 = <8>;
182 emmc_iot_8bit_mode: emmc_iot_8bit_mode {
184 groups = "ephy4_1_pad";
185 function = "digital";
194 groups = "sd router";
200 function = "sdxc d5 d4";
205 function = "sdxc d6";
210 function = "sdxc d7";
215 drive-strength-4g = <8>;
220 watchdog: watchdog@100 {
221 compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
224 resets = <&rstctrl MT7628_TIMER_RST>;
227 interrupt-parent = <&intc>;
231 intc: interrupt-controller@200 {
232 compatible = "ralink,rt2880-intc";
235 interrupt-controller;
236 #interrupt-cells = <1>;
238 resets = <&rstctrl MT7628_INT_RST>;
239 reset-names = "intc";
241 interrupt-parent = <&cpuintc>;
244 ralink,intc-registers = <0x9c 0xa0
249 memory-controller@300 {
250 compatible = "ralink,mt7620a-memc";
255 #address-cells = <1>;
258 compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
261 resets = <&rstctrl MT7628_PIO_RST>;
264 interrupt-parent = <&intc>;
269 compatible = "mtk,mt7621-gpio-bank";
276 compatible = "mtk,mt7621-gpio-bank";
283 compatible = "mtk,mt7621-gpio-bank";
290 compatible = "ralink,mt7621-spi";
293 resets = <&rstctrl MT7628_SPI_RST>;
296 #address-cells = <1>;
299 clocks = <&clkctrl CLK_SPI>;
302 uart0: uartlite@c00 {
303 compatible = "mediatek,hsuart", "ns16550a";
306 pinctrl-names = "default";
307 pinctrl-0 = <&uart0_pins>;
309 clocks = <&clkctrl CLK_UART0>;
311 resets = <&rstctrl MT7628_UART0_RST>;
312 reset-names = "uart0";
314 interrupt-parent = <&intc>;
321 compatible = "mediatek,hsuart", "ns16550a";
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart1_pins>;
327 clocks = <&clkctrl CLK_UART1>;
329 resets = <&rstctrl MT7628_UART1_RST>;
330 reset-names = "uart1";
332 interrupt-parent = <&intc>;
339 compatible = "mediatek,hsuart", "ns16550a";
342 pinctrl-names = "default";
343 pinctrl-0 = <&uart2_pins>;
345 clocks = <&clkctrl CLK_UART2>;
347 resets = <&rstctrl MT7628_UART2_RST>;
348 reset-names = "uart2";
350 interrupt-parent = <&intc>;
358 compatible = "mediatek,mt7628-eth";
359 reg = <0x10100000 0x10000
362 resets = <&rstctrl MT7628_EPHY_RST>;
363 reset-names = "ephy";
368 usb_phy: usb-phy@10120000 {
369 compatible = "mediatek,mt7628-usbphy";
370 reg = <0x10120000 0x1000>;
374 ralink,sysctl = <&sysc>;
376 resets = <&rstctrl MT7628_UPHY_RST>;
379 clocks = <&clkctrl CLK_UPHY>;
384 compatible = "generic-ehci";
385 reg = <0x101c0000 0x1000>;
390 interrupt-parent = <&intc>;
395 compatible = "mediatek,mt7620-mmc";
396 reg = <0x10130000 0x4000>;
400 clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
401 clock-names = "source", "hclk";
403 resets = <&rstctrl MT7628_SDXC_RST>;