arch/mips/dts/brcm,bcm6362.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Ã\81lvaro FernÃ¡ndez Rojas <noltari@gmail.com>
   4  */
   5
   6 #include <dt-bindings/clock/bcm6362-clock.h>
   7 #include <dt-bindings/dma/bcm6362-dma.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/power-domain/bcm6362-power-domain.h>
  10 #include <dt-bindings/reset/bcm6362-reset.h>
  11 #include "skeleton.dtsi"
  12
  13 / {
  14         compatible = "brcm,bcm6362";
  15
  16         aliases {
  17                 spi0 = &lsspi;
  18                 spi1 = &hsspi;
  19         };
  20
  21         cpus {
  22                 reg = <0x10000000 0x4>;
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25                 u-boot,dm-pre-reloc;
  26
  27                 cpu@0 {
  28                         compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
  29                         device_type = "cpu";
  30                         reg = <0>;
  31                         u-boot,dm-pre-reloc;
  32                 };
  33
  34                 cpu@1 {
  35                         compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
  36                         device_type = "cpu";
  37                         reg = <1>;
  38                         u-boot,dm-pre-reloc;
  39                 };
  40         };
  41
  42         clocks {
  43                 compatible = "simple-bus";
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46                 u-boot,dm-pre-reloc;
  47
  48                 hsspi_pll: hsspi-pll {
  49                         compatible = "fixed-clock";
  50                         #clock-cells = <0>;
  51                         clock-frequency = <133333333>;
  52                 };
  53
  54                 periph_osc: periph-osc {
  55                         compatible = "fixed-clock";
  56                         #clock-cells = <0>;
  57                         clock-frequency = <50000000>;
  58                         u-boot,dm-pre-reloc;
  59                 };
  60
  61                 periph_clk: periph-clk {
  62                         compatible = "brcm,bcm6345-clk";
  63                         reg = <0x10000004 0x4>;
  64                         #clock-cells = <1>;
  65                 };
  66         };
  67
  68         ubus {
  69                 compatible = "simple-bus";
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72                 u-boot,dm-pre-reloc;
  73
  74                 pll_cntl: syscon@10000008 {
  75                         compatible = "syscon";
  76                         reg = <0x10000008 0x4>;
  77                 };
  78
  79                 syscon-reboot {
  80                         compatible = "syscon-reboot";
  81                         regmap = <&pll_cntl>;
  82                         offset = <0x0>;
  83                         mask = <0x1>;
  84                 };
  85
  86                 periph_rst: reset-controller@10000010 {
  87                         compatible = "brcm,bcm6345-reset";
  88                         reg = <0x10000010 0x4>;
  89                         #reset-cells = <1>;
  90                 };
  91
  92                 wdt: watchdog@1000005c {
  93                         compatible = "brcm,bcm6345-wdt";
  94                         reg = <0x1000005c 0xc>;
  95                         clocks = <&periph_osc>;
  96                 };
  97
  98                 wdt-reboot {
  99                         compatible = "wdt-reboot";
 100                         wdt = <&wdt>;
 101                 };
 102
 103                 gpio1: gpio-controller@10000080 {
 104                         compatible = "brcm,bcm6345-gpio";
 105                         reg = <0x10000080 0x4>, <0x10000088 0x4>;
 106                         gpio-controller;
 107                         #gpio-cells = <2>;
 108                         ngpios = <16>;
 109
 110                         status = "disabled";
 111                 };
 112
 113                 gpio0: gpio-controller@10000084 {
 114                         compatible = "brcm,bcm6345-gpio";
 115                         reg = <0x10000084 0x4>, <0x1000008c 0x4>;
 116                         gpio-controller;
 117                         #gpio-cells = <2>;
 118
 119                         status = "disabled";
 120                 };
 121
 122                 uart0: serial@10000100 {
 123                         compatible = "brcm,bcm6345-uart";
 124                         reg = <0x10000100 0x18>;
 125                         clocks = <&periph_osc>;
 126
 127                         status = "disabled";
 128                 };
 129
 130                 uart1: serial@10000120 {
 131                         compatible = "brcm,bcm6345-uart";
 132                         reg = <0x10000120 0x18>;
 133                         clocks = <&periph_osc>;
 134
 135                         status = "disabled";
 136                 };
 137
 138                 nand: nand-controller@10000200 {
 139                         #address-cells = <1>;
 140                         #size-cells = <0>;
 141                         compatible = "brcm,nand-bcm6368",
 142                                      "brcm,brcmnand-v2.2",
 143                                      "brcm,brcmnand";
 144                         reg-names = "nand",
 145                                     "nand-cache",
 146                                     "nand-int-base";
 147                         reg = <0x10000200 0x180>,
 148                               <0x10000600 0x200>,
 149                               <0x100000b0 0x10>;
 150                         clocks = <&periph_clk BCM6362_CLK_NAND>;
 151                         clock-names = "nand";
 152
 153                         status = "disabled";
 154                 };
 155
 156                 lsspi: spi@10000800 {
 157                         compatible = "brcm,bcm6358-spi";
 158                         reg = <0x10000800 0x70c>;
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                         clocks = <&periph_clk BCM6362_CLK_SPI>;
 162                         resets = <&periph_rst BCM6362_RST_SPI>;
 163                         spi-max-frequency = <20000000>;
 164                         num-cs = <8>;
 165
 166                         status = "disabled";
 167                 };
 168
 169                 hsspi: spi@10001000 {
 170                         compatible = "brcm,bcm6328-hsspi";
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         reg = <0x10001000 0x600>;
 174                         clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>;
 175                         clock-names = "hsspi", "pll";
 176                         resets = <&periph_rst BCM6362_RST_SPI>;
 177                         spi-max-frequency = <50000000>;
 178                         num-cs = <8>;
 179
 180                         status = "disabled";
 181                 };
 182
 183                 leds: led-controller@10001900 {
 184                         compatible = "brcm,bcm6328-leds";
 185                         reg = <0x10001900 0x24>;
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188
 189                         status = "disabled";
 190                 };
 191
 192                 periph_pwr: power-controller@10001848 {
 193                         compatible = "brcm,bcm6328-power-domain";
 194                         reg = <0x10001848 0x4>;
 195                         #power-domain-cells = <1>;
 196                 };
 197
 198                 ehci: usb-controller@10002500 {
 199                         compatible = "brcm,bcm6362-ehci", "generic-ehci";
 200                         reg = <0x10002500 0x100>;
 201                         phys = <&usbh>;
 202                         big-endian;
 203
 204                         status = "disabled";
 205                 };
 206
 207                 ohci: usb-controller@10002600 {
 208                         compatible = "brcm,bcm6362-ohci", "generic-ohci";
 209                         reg = <0x10002600 0x100>;
 210                         phys = <&usbh>;
 211                         big-endian;
 212
 213                         status = "disabled";
 214                 };
 215
 216                 usbh: usb-phy@10002700 {
 217                         compatible = "brcm,bcm6368-usbh";
 218                         reg = <0x10002700 0x38>;
 219                         #phy-cells = <0>;
 220                         clocks = <&periph_clk BCM6362_CLK_USBH>;
 221                         clock-names = "usbh";
 222                         power-domains = <&periph_pwr BCM6362_PWR_USBH>;
 223                         resets = <&periph_rst BCM6362_RST_USBH>;
 224
 225                         status = "disabled";
 226                 };
 227
 228                 memory-controller@10003000 {
 229                         compatible = "brcm,bcm6328-mc";
 230                         reg = <0x10003000 0x864>;
 231                         u-boot,dm-pre-reloc;
 232                 };
 233
 234                 iudma: dma-controller@1000d800 {
 235                         compatible = "brcm,bcm6368-iudma";
 236                         reg = <0x1000d800 0x80>,
 237                               <0x1000da00 0x80>,
 238                               <0x1000dc00 0x80>;
 239                         reg-names = "dma",
 240                                     "dma-channels",
 241                                     "dma-sram";
 242                         #dma-cells = <1>;
 243                         dma-channels = <8>;
 244                 };
 245
 246                 enet: ethernet@10e00000 {
 247                         compatible = "brcm,bcm6368-enet";
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         reg = <0x10e00000 0x10000>;
 251                         clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,
 252                                  <&periph_clk BCM6362_CLK_SWPKT_SAR>,
 253                                  <&periph_clk BCM6362_CLK_ROBOSW>;
 254                         resets = <&periph_rst BCM6362_RST_ENETSW>,
 255                                  <&periph_rst BCM6362_RST_EPHY>;
 256                         dmas = <&iudma BCM6362_DMA_ENETSW_RX>,
 257                                <&iudma BCM6362_DMA_ENETSW_TX>;
 258                         dma-names = "rx",
 259                                     "tx";
 260                         brcm,num-ports = <6>;
 261
 262                         status = "disabled";
 263                 };
 264         };
 265 };