1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select ROM_EXCEPTION_VECTORS
18 select SUPPORTS_BIG_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select SUPPORTS_LITTLE_ENDIAN
29 select DYNAMIC_IO_PORT_BASE
31 select MIPS_INSERT_BOOT_CONFIG
32 select MIPS_L1_CACHE_SHIFT_6
36 select ROM_EXCEPTION_VECTORS
37 select SUPPORTS_BIG_ENDIAN
38 select SUPPORTS_CPU_MIPS32_R1
39 select SUPPORTS_CPU_MIPS32_R2
40 select SUPPORTS_CPU_MIPS32_R6
41 select SUPPORTS_CPU_MIPS64_R1
42 select SUPPORTS_CPU_MIPS64_R2
43 select SUPPORTS_CPU_MIPS64_R6
44 select SUPPORTS_LITTLE_ENDIAN
50 select ROM_EXCEPTION_VECTORS
51 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_CPU_MIPS32_R1
53 select SUPPORTS_CPU_MIPS32_R2
54 select SYS_MIPS_CACHE_INIT_RAM_LOAD
57 bool "Support QCA/Atheros ath79"
63 bool "Support MSCC VCore-III"
68 bool "Support BMIPS SoCs"
78 bool "Support MediaTek MIPS platforms"
81 select DISPLAY_CPUINFO
93 select LAST_STAGE_INIT
96 select ROM_EXCEPTION_VECTORS
97 select SUPPORTS_CPU_MIPS32_R1
98 select SUPPORTS_CPU_MIPS32_R2
99 select SUPPORTS_LITTLE_ENDIAN
103 bool "Support Ingenic JZ47xx"
109 bool "Support Microchip PIC32"
115 bool "Support Boston"
119 select MIPS_L1_CACHE_SHIFT_6
121 select OF_BOARD_SETUP
123 select ROM_EXCEPTION_VECTORS
124 select SUPPORTS_BIG_ENDIAN
125 select SUPPORTS_CPU_MIPS32_R1
126 select SUPPORTS_CPU_MIPS32_R2
127 select SUPPORTS_CPU_MIPS32_R6
128 select SUPPORTS_CPU_MIPS64_R1
129 select SUPPORTS_CPU_MIPS64_R2
130 select SUPPORTS_CPU_MIPS64_R6
131 select SUPPORTS_LITTLE_ENDIAN
134 config TARGET_XILFPGA
135 bool "Support Imagination Xilfpga"
140 select MIPS_L1_CACHE_SHIFT_4
142 select ROM_EXCEPTION_VECTORS
143 select SUPPORTS_CPU_MIPS32_R1
144 select SUPPORTS_CPU_MIPS32_R2
145 select SUPPORTS_LITTLE_ENDIAN
148 This supports IMGTEC MIPSfpga platform
152 source "board/imgtec/boston/Kconfig"
153 source "board/imgtec/malta/Kconfig"
154 source "board/imgtec/xilfpga/Kconfig"
155 source "board/qemu-mips/Kconfig"
156 source "arch/mips/mach-ath79/Kconfig"
157 source "arch/mips/mach-mscc/Kconfig"
158 source "arch/mips/mach-bmips/Kconfig"
159 source "arch/mips/mach-jz47xx/Kconfig"
160 source "arch/mips/mach-pic32/Kconfig"
161 source "arch/mips/mach-mtmips/Kconfig"
166 prompt "Endianness selection"
168 Some MIPS boards can be configured for either little or big endian
169 byte order. These modes require different U-Boot images. In general there
170 is one preferred byteorder for a particular system but some systems are
171 just as commonly used in the one or the other endianness.
173 config SYS_BIG_ENDIAN
175 depends on SUPPORTS_BIG_ENDIAN
177 config SYS_LITTLE_ENDIAN
179 depends on SUPPORTS_LITTLE_ENDIAN
184 prompt "CPU selection"
185 default CPU_MIPS32_R2
188 bool "MIPS32 Release 1"
189 depends on SUPPORTS_CPU_MIPS32_R1
192 Choose this option to build an U-Boot for release 1 through 5 of the
196 bool "MIPS32 Release 2"
197 depends on SUPPORTS_CPU_MIPS32_R2
200 Choose this option to build an U-Boot for release 2 through 5 of the
204 bool "MIPS32 Release 6"
205 depends on SUPPORTS_CPU_MIPS32_R6
208 Choose this option to build an U-Boot for release 6 or later of the
212 bool "MIPS64 Release 1"
213 depends on SUPPORTS_CPU_MIPS64_R1
216 Choose this option to build a kernel for release 1 through 5 of the
220 bool "MIPS64 Release 2"
221 depends on SUPPORTS_CPU_MIPS64_R2
224 Choose this option to build a kernel for release 2 through 5 of the
228 bool "MIPS64 Release 6"
229 depends on SUPPORTS_CPU_MIPS64_R6
232 Choose this option to build a kernel for release 6 or later of the
239 config ROM_EXCEPTION_VECTORS
240 bool "Build U-Boot image with exception vectors"
242 Enable this to include exception vectors in the U-Boot image. This is
243 required if the U-Boot entry point is equal to the address of the
244 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
245 U-Boot booted from parallel NOR flash).
246 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
247 In that case the image size will be reduced by 0x500 bytes.
250 hex "MIPS CM GCR Base Address"
252 default 0x16100000 if TARGET_BOSTON
255 The physical base address at which to map the MIPS Coherence Manager
256 Global Configuration Registers (GCRs). This should be set such that
257 the GCRs occupy a region of the physical address space which is
258 otherwise unused, or at minimum that software doesn't need to access.
260 config MIPS_CACHE_INDEX_BASE
261 hex "Index base address for cache initialisation"
262 default 0x80000000 if CPU_MIPS32
263 default 0xffffffff80000000 if CPU_MIPS64
265 This is the base address for a memory block, which is used for
266 initialising the cache lines. This is also the base address of a memory
267 block which is used for loading and filling cache lines when
268 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
269 Normally this is CKSEG0. If the MIPS system needs to move this block
270 to some SRAM or ScratchPad RAM, adapt this option accordingly.
272 config MIPS_RELOCATION_TABLE_SIZE
273 hex "Relocation table size"
277 A table of relocation data will be appended to the U-Boot binary
278 and parsed in relocate_code() to fix up all offsets in the relocated
281 This option allows the amount of space reserved for the table to be
282 adjusted in a range from 256 up to 64k. The default is 32k and should
283 be ok in most cases. Reduce this value to shrink the size of U-Boot
286 The build will fail and a valid size suggested if this is too small.
288 If unsure, leave at the default value.
290 config RESTORE_EXCEPTION_VECTOR_BASE
291 bool "Restore exception vector base before booting linux kernel"
294 In U-Boot the exception vector base will be moved to top of memory,
295 to be used to display register dump when exception occurs.
296 But some old linux kernel does not honor the base set in CP0_EBASE.
297 A modified exception vector base will cause kernel crash.
299 This option will restore the exception vector base to its previous
304 config OVERRIDE_EXCEPTION_VECTOR_BASE
305 bool "Override the exception vector base to be restored"
306 depends on RESTORE_EXCEPTION_VECTOR_BASE
309 Enable this option if you want to use a different exception vector
310 base rather than the previously saved one.
312 config NEW_EXCEPTION_VECTOR_BASE
313 hex "New exception vector base"
314 depends on OVERRIDE_EXCEPTION_VECTOR_BASE
315 range 0x80000000 0xbffff000
318 The exception vector base to be restored before booting linux kernel
320 config SPL_LOADER_SUPPORT
324 Enable this option if you want to use SPL loaders without DM enabled.
328 menu "OS boot interface"
330 config MIPS_BOOT_CMDLINE_LEGACY
331 bool "Hand over legacy command line to Linux kernel"
334 Enable this option if you want U-Boot to hand over the Yamon-style
335 command line to the kernel. All bootargs will be prepared as argc/argv
336 compatible list. The argument count (argc) is stored in register $a0.
337 The address of the argument list (argv) is stored in register $a1.
339 config MIPS_BOOT_ENV_LEGACY
340 bool "Hand over legacy environment to Linux kernel"
343 Enable this option if you want U-Boot to hand over the Yamon-style
344 environment to the kernel. Information like memory size, initrd
345 address and size will be prepared as zero-terminated key/value list.
346 The address of the environment is stored in register $a2.
349 bool "Hand over a flattened device tree to Linux kernel"
352 Enable this option if you want U-Boot to hand over a flattened
353 device tree to the kernel. According to UHI register $a0 will be set
354 to -2 and the FDT address is stored in $a1.
358 config SUPPORTS_BIG_ENDIAN
361 config SUPPORTS_LITTLE_ENDIAN
364 config SUPPORTS_CPU_MIPS32_R1
367 config SUPPORTS_CPU_MIPS32_R2
370 config SUPPORTS_CPU_MIPS32_R6
373 config SUPPORTS_CPU_MIPS64_R1
376 config SUPPORTS_CPU_MIPS64_R2
379 config SUPPORTS_CPU_MIPS64_R6
384 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
388 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
393 config MIPS_TUNE_14KC
396 config MIPS_TUNE_24KC
399 config MIPS_TUNE_34KC
402 config MIPS_TUNE_74KC
414 config SYS_MIPS_CACHE_INIT_RAM_LOAD
417 config MIPS_INIT_STACK_IN_SRAM
421 Select this if the initial stack frame could be setup in SRAM.
422 Normally the initial stack frame is set up in DRAM which is often
423 only available after lowlevel_init. With this option the initial
424 stack frame and the early C environment is set up before
425 lowlevel_init. Thus lowlevel_init does not need to be implemented
428 config MIPS_SRAM_INIT
431 depends on MIPS_INIT_STACK_IN_SRAM
433 Select this if the SRAM for initial stack needs to be initialized
434 before it can be used. If enabled, a function mips_sram_init() will
435 be called just before setup_stack_gd.
437 config SYS_DCACHE_SIZE
441 The total size of the L1 Dcache, if known at compile time.
443 config SYS_DCACHE_LINE_SIZE
447 The size of L1 Dcache lines, if known at compile time.
449 config SYS_ICACHE_SIZE
453 The total size of the L1 ICache, if known at compile time.
455 config SYS_ICACHE_LINE_SIZE
459 The size of L1 Icache lines, if known at compile time.
461 config SYS_SCACHE_LINE_SIZE
465 The size of L2 cache lines, if known at compile time.
468 config SYS_CACHE_SIZE_AUTO
469 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
470 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
471 SYS_SCACHE_LINE_SIZE = 0
473 Select this (or let it be auto-selected by not defining any cache
474 sizes) in order to allow U-Boot to automatically detect the sizes
475 of caches at runtime. This has a small cost in code size & runtime
476 so if you know the cache configuration for your system at compile
477 time it would be beneficial to configure it.
479 config MIPS_L1_CACHE_SHIFT_4
482 config MIPS_L1_CACHE_SHIFT_5
485 config MIPS_L1_CACHE_SHIFT_6
488 config MIPS_L1_CACHE_SHIFT_7
491 config MIPS_L1_CACHE_SHIFT
493 default "7" if MIPS_L1_CACHE_SHIFT_7
494 default "6" if MIPS_L1_CACHE_SHIFT_6
495 default "5" if MIPS_L1_CACHE_SHIFT_5
496 default "4" if MIPS_L1_CACHE_SHIFT_4
502 Select this if your system includes an L2 cache and you want U-Boot
503 to initialise & maintain it.
505 config DYNAMIC_IO_PORT_BASE
511 Select this if your system contains a MIPS Coherence Manager and you
512 wish U-Boot to configure it or make use of it to retrieve system
513 information such as cache configuration.
515 config MIPS_INSERT_BOOT_CONFIG
519 Enable this to insert some board-specific boot configuration in
520 the U-Boot binary at offset 0x10.
522 config MIPS_BOOT_CONFIG_WORD0
524 depends on MIPS_INSERT_BOOT_CONFIG
525 default 0x420 if TARGET_MALTA
528 Value which is inserted as boot config word 0.
530 config MIPS_BOOT_CONFIG_WORD1
532 depends on MIPS_INSERT_BOOT_CONFIG
535 Value which is inserted as boot config word 1.