arch/arm/mach-zynqmp/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 - 2016 Xilinx, Inc.
   4  *
   5  * Michal Simek <michal.simek@xilinx.com>
   6  */
   7
   8 #include <common.h>
   9 #include <debug_uart.h>
  10 #include <spl.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/spl.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 void board_init_f(ulong dummy)
  18 {
  19         board_early_init_f();
  20         board_early_init_r();
  21
  22 #ifdef CONFIG_DEBUG_UART
  23         /* Uart debug for sure */
  24         debug_uart_init();
  25         puts("Debug uart enabled\n"); /* or printch() */
  26 #endif
  27         /* Delay is required for clocks to be propagated */
  28         udelay(1000000);
  29
  30         debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end);
  31         /* Clear the BSS */
  32         memset(__bss_start, 0, __bss_end - __bss_start);
  33
  34         /* No need to call timer init - it is empty for ZynqMP */
  35         board_init_r(NULL, 0);
  36 }
  37
  38 static void ps_mode_reset(ulong mode)
  39 {
  40         writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  41                &crlapb_base->boot_pin_ctrl);
  42         udelay(5);
  43         writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
  44                mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  45                &crlapb_base->boot_pin_ctrl);
  46 }
  47
  48 /*
  49  * Set default PS_MODE1 which is used for USB ULPI phy reset
  50  * Also other resets can be connected to this certain pin
  51  */
  52 #ifndef MODE_RESET
  53 # define MODE_RESET     PS_MODE1
  54 #endif
  55
  56 #ifdef CONFIG_SPL_BOARD_INIT
  57 void spl_board_init(void)
  58 {
  59         preloader_console_init();
  60         ps_mode_reset(MODE_RESET);
  61         board_init();
  62 }
  63 #endif
  64
  65 u32 spl_boot_device(void)
  66 {
  67         u32 reg = 0;
  68         u8 bootmode;
  69
  70 #if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
  71         /* Change default boot mode at run-time */
  72         writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
  73                &crlapb_base->boot_mode);
  74 #endif
  75
  76         reg = readl(&crlapb_base->boot_mode);
  77         if (reg >> BOOT_MODE_ALT_SHIFT)
  78                 reg >>= BOOT_MODE_ALT_SHIFT;
  79
  80         bootmode = reg & BOOT_MODES_MASK;
  81
  82         switch (bootmode) {
  83         case JTAG_MODE:
  84                 return BOOT_DEVICE_RAM;
  85 #ifdef CONFIG_SPL_MMC_SUPPORT
  86         case SD_MODE1:
  87         case SD1_LSHFT_MODE: /* not working on silicon v1 */
  88 /* if both controllers enabled, then these two are the second controller */
  89 #ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
  90                 return BOOT_DEVICE_MMC2;
  91 /* else, fall through, the one SDHCI controller that is enabled is number 1 */
  92 #endif
  93         case SD_MODE:
  94         case EMMC_MODE:
  95                 return BOOT_DEVICE_MMC1;
  96 #endif
  97 #ifdef CONFIG_SPL_DFU
  98         case USB_MODE:
  99                 return BOOT_DEVICE_DFU;
 100 #endif
 101 #ifdef CONFIG_SPL_SATA_SUPPORT
 102         case SW_SATA_MODE:
 103                 return BOOT_DEVICE_SATA;
 104 #endif
 105 #ifdef CONFIG_SPL_SPI_SUPPORT
 106         case QSPI_MODE_24BIT:
 107         case QSPI_MODE_32BIT:
 108                 return BOOT_DEVICE_SPI;
 109 #endif
 110         default:
 111                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 112                 break;
 113         }
 114
 115         return 0;
 116 }
 117
 118 #ifdef CONFIG_SPL_OS_BOOT
 119 int spl_start_uboot(void)
 120 {
 121         handoff_setup();
 122
 123         return 0;
 124 }
 125 #endif
 126
 127 #ifdef CONFIG_SPL_LOAD_FIT
 128 int board_fit_config_name_match(const char *name)
 129 {
 130         /* Just empty function now - can't decide what to choose */
 131         debug("%s: %s\n", __func__, name);
 132
 133         return 0;
 134 }
 135 #endif