arch/arm/mach-zynqmp/mp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <log.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/io.h>
  13
  14 #define LOCK            0
  15 #define SPLIT           1
  16
  17 #define HALT            0
  18 #define RELEASE         1
  19
  20 #define ZYNQMP_BOOTADDR_HIGH_MASK               0xFFFFFFFF
  21 #define ZYNQMP_R5_HIVEC_ADDR                    0xFFFF0000
  22 #define ZYNQMP_R5_LOVEC_ADDR                    0x0
  23 #define ZYNQMP_RPU_CFG_CPU_HALT_MASK            0x01
  24 #define ZYNQMP_RPU_CFG_HIVEC_MASK               0x04
  25 #define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK    0x08
  26 #define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK      0x40
  27 #define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK       0x10
  28
  29 #define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK     0x04
  30 #define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK      0x01
  31 #define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK      0x02
  32 #define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK   0x1000000
  33
  34 #define ZYNQMP_TCM_START_ADDRESS                0xFFE00000
  35 #define ZYNQMP_TCM_BOTH_SIZE                    0x40000
  36
  37 #define ZYNQMP_CORE_APU0        0
  38 #define ZYNQMP_CORE_APU3        3
  39
  40 #define ZYNQMP_MAX_CORES        6
  41
  42 int is_core_valid(unsigned int core)
  43 {
  44         if (core < ZYNQMP_MAX_CORES)
  45                 return 1;
  46
  47         return 0;
  48 }
  49
  50 int cpu_reset(u32 nr)
  51 {
  52         puts("Feature is not implemented.\n");
  53         return 0;
  54 }
  55
  56 static void set_r5_halt_mode(u8 halt, u8 mode)
  57 {
  58         u32 tmp;
  59
  60         tmp = readl(&rpu_base->rpu0_cfg);
  61         if (halt == HALT)
  62                 tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  63         else
  64                 tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  65         writel(tmp, &rpu_base->rpu0_cfg);
  66
  67         if (mode == LOCK) {
  68                 tmp = readl(&rpu_base->rpu1_cfg);
  69                 if (halt == HALT)
  70                         tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  71                 else
  72                         tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  73                 writel(tmp, &rpu_base->rpu1_cfg);
  74         }
  75 }
  76
  77 static void set_r5_tcm_mode(u8 mode)
  78 {
  79         u32 tmp;
  80
  81         tmp = readl(&rpu_base->rpu_glbl_ctrl);
  82         if (mode == LOCK) {
  83                 tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  84                 tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
  85                        ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
  86         } else {
  87                 tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  88                 tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
  89                        ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK);
  90         }
  91
  92         writel(tmp, &rpu_base->rpu_glbl_ctrl);
  93 }
  94
  95 static void set_r5_reset(u8 mode)
  96 {
  97         u32 tmp;
  98
  99         tmp = readl(&crlapb_base->rst_lpd_top);
 100         tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
 101                ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
 102
 103         if (mode == LOCK)
 104                 tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
 105
 106         writel(tmp, &crlapb_base->rst_lpd_top);
 107 }
 108
 109 static void release_r5_reset(u8 mode)
 110 {
 111         u32 tmp;
 112
 113         tmp = readl(&crlapb_base->rst_lpd_top);
 114         tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
 115                ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
 116
 117         if (mode == LOCK)
 118                 tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
 119
 120         writel(tmp, &crlapb_base->rst_lpd_top);
 121 }
 122
 123 static void enable_clock_r5(void)
 124 {
 125         u32 tmp;
 126
 127         tmp = readl(&crlapb_base->cpu_r5_ctrl);
 128         tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
 129         writel(tmp, &crlapb_base->cpu_r5_ctrl);
 130
 131         /* Give some delay for clock
 132          * to propagate */
 133         udelay(0x500);
 134 }
 135
 136 int cpu_disable(u32 nr)
 137 {
 138         if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
 139                 u32 val = readl(&crfapb_base->rst_fpd_apu);
 140                 val |= 1 << nr;
 141                 writel(val, &crfapb_base->rst_fpd_apu);
 142         } else {
 143                 set_r5_reset(LOCK);
 144         }
 145
 146         return 0;
 147 }
 148
 149 int cpu_status(u32 nr)
 150 {
 151         if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
 152                 u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
 153                 u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) +
 154                                       nr * 8);
 155                 u32 val = readl(&crfapb_base->rst_fpd_apu);
 156                 val &= 1 << nr;
 157                 printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n",
 158                        nr, val ? "OFF" : "ON" , addr_high, addr_low);
 159         } else {
 160                 u32 val = readl(&crlapb_base->rst_lpd_top);
 161                 val &= 1 << (nr - 4);
 162                 printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON");
 163         }
 164
 165         return 0;
 166 }
 167
 168 static void set_r5_start(u8 high)
 169 {
 170         u32 tmp;
 171
 172         tmp = readl(&rpu_base->rpu0_cfg);
 173         if (high)
 174                 tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
 175         else
 176                 tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
 177         writel(tmp, &rpu_base->rpu0_cfg);
 178
 179         tmp = readl(&rpu_base->rpu1_cfg);
 180         if (high)
 181                 tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
 182         else
 183                 tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
 184         writel(tmp, &rpu_base->rpu1_cfg);
 185 }
 186
 187 static void write_tcm_boot_trampoline(u32 boot_addr)
 188 {
 189         if (boot_addr) {
 190                 /*
 191                  * Boot trampoline is simple ASM code below.
 192                  *
 193                  *              b over;
 194                  *      label:
 195                  *      .word   0
 196                  *      over:   ldr     r0, =label
 197                  *              ldr     r1, [r0]
 198                  *              bx      r1
 199                  */
 200                 debug("Write boot trampoline for %x\n", boot_addr);
 201                 writel(0xea000000, ZYNQMP_TCM_START_ADDRESS);
 202                 writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4);
 203                 writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8);
 204                 writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc);
 205                 writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10);
 206                 writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for
 207         }
 208 }
 209
 210 void initialize_tcm(bool mode)
 211 {
 212         if (!mode) {
 213                 set_r5_tcm_mode(LOCK);
 214                 set_r5_halt_mode(HALT, LOCK);
 215                 enable_clock_r5();
 216                 release_r5_reset(LOCK);
 217         } else {
 218                 set_r5_tcm_mode(SPLIT);
 219                 set_r5_halt_mode(HALT, SPLIT);
 220                 enable_clock_r5();
 221                 release_r5_reset(SPLIT);
 222         }
 223 }
 224
 225 int cpu_release(u32 nr, int argc, char *const argv[])
 226 {
 227         if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
 228                 u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
 229                 /* HIGH */
 230                 writel((u32)(boot_addr >> 32),
 231                        ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8);
 232                 /* LOW */
 233                 writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK),
 234                        ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
 235
 236                 u32 val = readl(&crfapb_base->rst_fpd_apu);
 237                 val &= ~(1 << nr);
 238                 writel(val, &crfapb_base->rst_fpd_apu);
 239         } else {
 240                 if (argc != 2) {
 241                         printf("Invalid number of arguments to release.\n");
 242                         printf("<addr> <mode>-Start addr lockstep or split\n");
 243                         return 1;
 244                 }
 245
 246                 u32 boot_addr = simple_strtoul(argv[0], NULL, 16);
 247                 u32 boot_addr_uniq = 0;
 248                 if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR ||
 249                       boot_addr == ZYNQMP_R5_HIVEC_ADDR)) {
 250                         printf("Using TCM jump trampoline for address 0x%x\n",
 251                                boot_addr);
 252                         /* Save boot address for later usage */
 253                         boot_addr_uniq = boot_addr;
 254                         /*
 255                          * R5 needs to start from LOVEC at TCM
 256                          * OCM will be probably occupied by ATF
 257                          */
 258                         boot_addr = ZYNQMP_R5_LOVEC_ADDR;
 259                 }
 260
 261                 /*
 262                  * Since we don't know where the user may have loaded the image
 263                  * for an R5 we have to flush all the data cache to ensure
 264                  * the R5 sees it.
 265                  */
 266                 flush_dcache_all();
 267
 268                 if (!strncmp(argv[1], "lockstep", 8)) {
 269                         printf("R5 lockstep mode\n");
 270                         set_r5_reset(LOCK);
 271                         set_r5_tcm_mode(LOCK);
 272                         set_r5_halt_mode(HALT, LOCK);
 273                         set_r5_start(boot_addr);
 274                         enable_clock_r5();
 275                         release_r5_reset(LOCK);
 276                         dcache_disable();
 277                         write_tcm_boot_trampoline(boot_addr_uniq);
 278                         dcache_enable();
 279                         set_r5_halt_mode(RELEASE, LOCK);
 280                 } else if (!strncmp(argv[1], "split", 5)) {
 281                         printf("R5 split mode\n");
 282                         set_r5_reset(SPLIT);
 283                         set_r5_tcm_mode(SPLIT);
 284                         set_r5_halt_mode(HALT, SPLIT);
 285                         set_r5_start(boot_addr);
 286                         enable_clock_r5();
 287                         release_r5_reset(SPLIT);
 288                         dcache_disable();
 289                         write_tcm_boot_trampoline(boot_addr_uniq);
 290                         dcache_enable();
 291                         set_r5_halt_mode(RELEASE, SPLIT);
 292                 } else {
 293                         printf("Unsupported mode\n");
 294                         return 1;
 295                 }
 296         }
 297
 298         return 0;
 299 }