arch/arm/mach-zynq/clk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
   4  * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
   5  */
   6 #include <clk.h>
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <malloc.h>
  11 #include <asm/arch/clk.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 static const char * const clk_names[clk_max] = {
  16         "armpll", "ddrpll", "iopll",
  17         "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
  18         "ddr2x", "ddr3x", "dci",
  19         "lqspi", "smc", "pcap", "gem0", "gem1",
  20         "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
  21         "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
  22         "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
  23         "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
  24         "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
  25         "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
  26         "smc_aper", "swdt", "dbg_trc", "dbg_apb"
  27 };
  28
  29 /**
  30  * set_cpu_clk_info() - Setup clock information
  31  *
  32  * This function is called from common code after relocation and sets up the
  33  * clock information.
  34  */
  35 int set_cpu_clk_info(void)
  36 {
  37         struct clk clk;
  38         struct udevice *dev;
  39         ulong rate;
  40         int i, ret;
  41
  42         ret = uclass_get_device_by_driver(UCLASS_CLK,
  43                 DM_GET_DRIVER(zynq_clk), &dev);
  44         if (ret)
  45                 return ret;
  46
  47         for (i = 0; i < 2; i++) {
  48                 clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
  49                 ret = clk_request(dev, &clk);
  50                 if (ret < 0)
  51                         return ret;
  52
  53                 rate = clk_get_rate(&clk) / 1000000;
  54                 if (i)
  55                         gd->bd->bi_ddr_freq = rate;
  56                 else
  57                         gd->bd->bi_arm_freq = rate;
  58
  59                 clk_free(&clk);
  60         }
  61         gd->bd->bi_dsp_freq = 0;
  62
  63         return 0;
  64 }
  65
  66 /**
  67  * soc_clk_dump() - Print clock frequencies
  68  * Returns zero on success
  69  *
  70  * Implementation for the clk dump command.
  71  */
  72 int soc_clk_dump(void)
  73 {
  74         struct udevice *dev;
  75         int i, ret;
  76
  77         ret = uclass_get_device_by_driver(UCLASS_CLK,
  78                 DM_GET_DRIVER(zynq_clk), &dev);
  79         if (ret)
  80                 return ret;
  81
  82         printf("clk\t\tfrequency\n");
  83         for (i = 0; i < clk_max; i++) {
  84                 const char *name = clk_names[i];
  85                 if (name) {
  86                         struct clk clk;
  87                         unsigned long rate;
  88
  89                         clk.id = i;
  90                         ret = clk_request(dev, &clk);
  91                         if (ret < 0)
  92                                 return ret;
  93
  94                         rate = clk_get_rate(&clk);
  95
  96                         clk_free(&clk);
  97
  98                         if ((rate == (unsigned long)-ENOSYS) ||
  99                             (rate == (unsigned long)-ENXIO))
 100                                 printf("%10s%20s\n", name, "unknown");
 101                         else
 102                                 printf("%10s%20lu\n", name, rate);
 103                 }
 104         }
 105
 106         return 0;
 107 }