arch/arm/mach-versal/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/armv8/mmu.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/sys_proto.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 #define VERSAL_MEM_MAP_USED     5
  16
  17 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  18
  19 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  20 #define TCM_MAP 1
  21 #else
  22 #define TCM_MAP 0
  23 #endif
  24
  25 /* +1 is end of list which needs to be empty */
  26 #define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  27
  28 static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
  29         {
  30                 .virt = 0x80000000UL,
  31                 .phys = 0x80000000UL,
  32                 .size = 0x70000000UL,
  33                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  34                          PTE_BLOCK_NON_SHARE |
  35                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  36         }, {
  37                 .virt = 0xf0000000UL,
  38                 .phys = 0xf0000000UL,
  39                 .size = 0x0fe00000UL,
  40                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  41                          PTE_BLOCK_NON_SHARE |
  42                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  43         }, {
  44                 .virt = 0x400000000UL,
  45                 .phys = 0x400000000UL,
  46                 .size = 0x200000000UL,
  47                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  48                          PTE_BLOCK_NON_SHARE |
  49                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  50         }, {
  51                 .virt = 0x600000000UL,
  52                 .phys = 0x600000000UL,
  53                 .size = 0x800000000UL,
  54                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  55                          PTE_BLOCK_INNER_SHARE
  56         }, {
  57                 .virt = 0xe00000000UL,
  58                 .phys = 0xe00000000UL,
  59                 .size = 0xf200000000UL,
  60                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  61                          PTE_BLOCK_NON_SHARE |
  62                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  63         }
  64 };
  65
  66 void mem_map_fill(void)
  67 {
  68         int banks = VERSAL_MEM_MAP_USED;
  69
  70 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  71         versal_mem_map[banks].virt = 0xffe00000UL;
  72         versal_mem_map[banks].phys = 0xffe00000UL;
  73         versal_mem_map[banks].size = 0x00200000UL;
  74         versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  75                                       PTE_BLOCK_INNER_SHARE;
  76         banks = banks + 1;
  77 #endif
  78
  79         for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  80                 /* Zero size means no more DDR that's this is end */
  81                 if (!gd->bd->bi_dram[i].size)
  82                         break;
  83
  84                 versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  85                 versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  86                 versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
  87                 versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  88                                               PTE_BLOCK_INNER_SHARE;
  89                 banks = banks + 1;
  90         }
  91 }
  92
  93 struct mm_region *mem_map = versal_mem_map;
  94
  95 u64 get_page_table_size(void)
  96 {
  97         return 0x14000;
  98 }
  99
 100 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
 101 int reserve_mmu(void)
 102 {
 103         tcm_init(TCM_LOCK);
 104         gd->arch.tlb_size = PGTABLE_SIZE;
 105         gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
 106
 107         return 0;
 108 }
 109 #endif