arch/arm/mach-uniphier/memconf.c

   1 /*
   2  * Copyright (C) 2011-2015 Panasonic Corporation
   3  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <linux/sizes.h>
  10 #include <asm/io.h>
  11 #include <mach/sg-regs.h>
  12
  13 static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
  14 {
  15         int size_mb = size / num;
  16         u32 ret;
  17
  18         switch (size_mb) {
  19         case SZ_64M:
  20                 ret = SG_MEMCONF_CH0_SZ_64M;
  21                 break;
  22         case SZ_128M:
  23                 ret = SG_MEMCONF_CH0_SZ_128M;
  24                 break;
  25         case SZ_256M:
  26                 ret = SG_MEMCONF_CH0_SZ_256M;
  27                 break;
  28         case SZ_512M:
  29                 ret = SG_MEMCONF_CH0_SZ_512M;
  30                 break;
  31         case SZ_1G:
  32                 ret = SG_MEMCONF_CH0_SZ_1G;
  33                 break;
  34         default:
  35                 BUG();
  36                 break;
  37         }
  38
  39         switch (num) {
  40         case 1:
  41                 ret |= SG_MEMCONF_CH0_NUM_1;
  42                 break;
  43         case 2:
  44                 ret |= SG_MEMCONF_CH0_NUM_2;
  45                 break;
  46         default:
  47                 BUG();
  48                 break;
  49         }
  50         return ret;
  51 }
  52
  53 static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
  54 {
  55         int size_mb = size / num;
  56         u32 ret;
  57
  58         switch (size_mb) {
  59         case SZ_64M:
  60                 ret = SG_MEMCONF_CH1_SZ_64M;
  61                 break;
  62         case SZ_128M:
  63                 ret = SG_MEMCONF_CH1_SZ_128M;
  64                 break;
  65         case SZ_256M:
  66                 ret = SG_MEMCONF_CH1_SZ_256M;
  67                 break;
  68         case SZ_512M:
  69                 ret = SG_MEMCONF_CH1_SZ_512M;
  70                 break;
  71         case SZ_1G:
  72                 ret = SG_MEMCONF_CH1_SZ_1G;
  73                 break;
  74         default:
  75                 BUG();
  76                 break;
  77         }
  78
  79         switch (num) {
  80         case 1:
  81                 ret |= SG_MEMCONF_CH1_NUM_1;
  82                 break;
  83         case 2:
  84                 ret |= SG_MEMCONF_CH1_NUM_2;
  85                 break;
  86         default:
  87                 BUG();
  88                 break;
  89         }
  90         return ret;
  91 }
  92
  93 void memconf_init(void)
  94 {
  95         u32 tmp;
  96
  97         /* Set DDR size */
  98         tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
  99         tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
 100 #if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
 101         tmp |= SG_MEMCONF_SPARSEMEM;
 102 #endif
 103         writel(tmp, SG_MEMCONF);
 104 }