1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2010-2015
5 * NVIDIA Corporation <www.nvidia.com>
8 /* Tegra20 Clock control functions */
15 #include <asm/arch/clock.h>
16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/clk_rst.h>
18 #include <asm/arch-tegra/timer.h>
21 #include <linux/delay.h>
24 * Clock types that we can use as a source. The Tegra20 has muxes for the
25 * peripheral clocks, and in most cases there are four options for the clock
26 * source. This gives us a clock 'type' and exploits what commonality exists
29 * Letters are obvious, except for T which means CLK_M, and S which means the
30 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
31 * datasheet) and PLL_M are different things. The former is the basic
32 * clock supplied to the SOC from an external oscillator. The latter is the
35 * See definitions in clock_id in the header file.
38 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
39 CLOCK_TYPE_MCPA, /* and so on */
43 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
48 CLOCK_TYPE_NONE = -1, /* invalid clock type */
52 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
56 * Clock source mux for each clock type. This just converts our enum into
57 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
58 * is special as it has 5 sources. Since it also has a different number of
59 * bits in its register for the source, we just handle it with a special
62 #define CLK(x) CLOCK_ID_ ## x
63 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
65 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
66 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
67 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
68 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
69 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
70 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
71 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
75 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
76 * not in the header file since it is for purely internal use - we want
77 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
78 * confusion bewteen PERIPH_ID_... and PERIPHC_...
80 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
83 * Note to SOC vendors: perhaps define a unified numbering for peripherals and
84 * use it for reset, clock enable, clock source/divider and even pinmuxing
87 enum periphc_internal_id {
104 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
162 * Clock type for each peripheral clock source. We put the name in each
163 * record just so it is easy to match things up
165 #define TYPE(name, type) type
166 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
168 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
169 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
170 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
171 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
172 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
173 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
174 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
175 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
178 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
179 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
180 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
181 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
182 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
183 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
184 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
185 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
188 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
189 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
190 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
191 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
192 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
193 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
194 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
195 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
198 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
199 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
200 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
201 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
202 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
203 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
204 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
205 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
208 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
209 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
211 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
212 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
213 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
214 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
215 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
218 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
219 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
220 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
221 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
222 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
223 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
224 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
225 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
228 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
229 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
230 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
231 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
232 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
233 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
237 * This array translates a periph_id to a periphc_internal_id
239 * Not present/matched up:
240 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
241 * SPDIF - which is both 0x08 and 0x0c
244 #define NONE(name) (-1)
245 #define OFFSET(name, value) PERIPHC_ ## name
246 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
255 PERIPHC_UART2, /* and vfir 0x68 */
260 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
287 /* Middle word: 63:32 */
299 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
309 PERIPHC_TVO, /* also CVE 0x40 */
327 /* Upper word 95:64 */
362 * PLL divider shift/mask tables for all PLL IDs.
364 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
367 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
368 * If lock_ena or lock_det are >31, they're not used in that PLL.
371 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
372 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
373 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
374 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
375 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
376 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
377 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
378 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
379 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
380 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
381 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
382 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
383 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
384 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
385 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
386 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
387 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
388 .lock_ena = 18, .lock_det = 0, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS */
392 * Get the oscillator frequency, from the corresponding hardware configuration
393 * field. T20 has 4 frequencies that it supports.
395 enum clock_osc_freq clock_get_osc_freq(void)
397 struct clk_rst_ctlr *clkrst =
398 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
401 reg = readl(&clkrst->crc_osc_ctrl);
402 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
405 /* Returns a pointer to the clock source register for a peripheral */
406 u32 *get_periph_source_reg(enum periph_id periph_id)
408 struct clk_rst_ctlr *clkrst =
409 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
410 enum periphc_internal_id internal_id;
412 assert(clock_periph_id_isvalid(periph_id));
413 internal_id = periph_id_to_internal_id[periph_id];
414 assert(internal_id != -1);
415 return &clkrst->crc_clk_src[internal_id];
418 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
419 int *divider_bits, int *type)
421 enum periphc_internal_id internal_id;
423 if (!clock_periph_id_isvalid(periph_id))
426 internal_id = periph_id_to_internal_id[periph_id];
427 if (!periphc_internal_id_isvalid(internal_id))
430 *type = clock_periph_type[internal_id];
431 if (!clock_type_id_isvalid(*type))
435 * Special cases here for the clock with a 4-bit source mux and I2C
436 * with its 16-bit divisor
438 if (*type == CLOCK_TYPE_PCXTS)
439 *mux_bits = MASK_BITS_31_28;
441 *mux_bits = MASK_BITS_31_30;
442 if (*type == CLOCK_TYPE_PCMT16)
450 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
452 enum periphc_internal_id internal_id;
455 if (!clock_periph_id_isvalid(periph_id))
456 return CLOCK_ID_NONE;
458 internal_id = periph_id_to_internal_id[periph_id];
459 if (!periphc_internal_id_isvalid(internal_id))
460 return CLOCK_ID_NONE;
462 type = clock_periph_type[internal_id];
463 if (!clock_type_id_isvalid(type))
464 return CLOCK_ID_NONE;
466 return clock_source[type][source];
470 * Given a peripheral ID and the required source clock, this returns which
471 * value should be programmed into the source mux for that peripheral.
473 * There is special code here to handle the one source type with 5 sources.
475 * @param periph_id peripheral to start
476 * @param source PLL id of required parent clock
477 * @param mux_bits Set to number of bits in mux register: 2 or 4
478 * @param divider_bits Set to number of divider bits (8 or 16)
479 * @return mux value (0-4, or -1 if not found)
481 int get_periph_clock_source(enum periph_id periph_id,
482 enum clock_id parent, int *mux_bits, int *divider_bits)
484 enum clock_type_id type;
487 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
490 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
491 if (clock_source[type][mux] == parent)
495 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
496 * which is not in our table. If not, then they are asking for a
497 * source which this peripheral can't access through its mux.
499 assert(type == CLOCK_TYPE_PCXTS);
500 assert(parent == CLOCK_ID_SFROM32KHZ);
501 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
502 return 4; /* mux value for this clock */
504 /* if we get here, either us or the caller has made a mistake */
505 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
510 void clock_set_enable(enum periph_id periph_id, int enable)
512 struct clk_rst_ctlr *clkrst =
513 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
514 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
517 /* Enable/disable the clock to this peripheral */
518 assert(clock_periph_id_isvalid(periph_id));
521 reg |= PERIPH_MASK(periph_id);
523 reg &= ~PERIPH_MASK(periph_id);
527 void reset_set_enable(enum periph_id periph_id, int enable)
529 struct clk_rst_ctlr *clkrst =
530 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
531 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
534 /* Enable/disable reset to the peripheral */
535 assert(clock_periph_id_isvalid(periph_id));
538 reg |= PERIPH_MASK(periph_id);
540 reg &= ~PERIPH_MASK(periph_id);
544 #if CONFIG_IS_ENABLED(OF_CONTROL)
546 * Convert a device tree clock ID to our peripheral ID. They are mostly
547 * the same but we are very cautious so we check that a valid clock ID is
550 * @param clk_id Clock ID according to tegra20 device tree binding
551 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
553 enum periph_id clk_id_to_periph_id(int clk_id)
555 if (clk_id > PERIPH_ID_COUNT)
556 return PERIPH_ID_NONE;
559 case PERIPH_ID_RESERVED1:
560 case PERIPH_ID_RESERVED2:
561 case PERIPH_ID_RESERVED30:
562 case PERIPH_ID_RESERVED35:
563 case PERIPH_ID_RESERVED56:
564 case PERIPH_ID_PCIEXCLK:
565 case PERIPH_ID_RESERVED76:
566 case PERIPH_ID_RESERVED77:
567 case PERIPH_ID_RESERVED78:
568 case PERIPH_ID_RESERVED79:
569 case PERIPH_ID_RESERVED80:
570 case PERIPH_ID_RESERVED81:
571 case PERIPH_ID_RESERVED82:
572 case PERIPH_ID_RESERVED83:
573 case PERIPH_ID_RESERVED91:
574 return PERIPH_ID_NONE;
579 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
581 void clock_early_init(void)
584 * PLLP output frequency set to 216MHz
585 * PLLC output frequency set to 600Mhz
587 * TODO: Can we calculate these values instead of hard-coding?
589 switch (clock_get_osc_freq()) {
590 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
591 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
592 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
595 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
596 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
597 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
600 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
601 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
602 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
604 case CLOCK_OSC_FREQ_19_2:
607 * These are not supported. It is too early to print a
608 * message and the UART likely won't work anyway due to the
609 * oscillator being wrong.
615 void arch_timer_init(void)
619 #define PMC_SATA_PWRGT 0x1ac
620 #define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
621 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
623 #define PLLE_SS_CNTL 0x68
624 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
625 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
626 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
627 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
628 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
629 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
631 #define PLLE_BASE 0x0e8
632 #define PLLE_BASE_ENABLE_CML (1 << 31)
633 #define PLLE_BASE_ENABLE (1 << 30)
634 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
635 #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
636 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
637 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
639 #define PLLE_MISC 0x0ec
640 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
641 #define PLLE_MISC_PLL_READY (1 << 15)
642 #define PLLE_MISC_LOCK (1 << 11)
643 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
644 #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
646 static int tegra_plle_train(void)
648 unsigned int timeout = 2000;
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
652 value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
656 value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
660 value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
664 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
665 if (value & PLLE_MISC_PLL_READY)
672 pr_err("timeout waiting for PLLE to become ready");
679 int tegra_plle_enable(void)
681 unsigned int timeout = 1000;
685 /* disable PLLE clock */
686 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
687 value &= ~PLLE_BASE_ENABLE_CML;
688 value &= ~PLLE_BASE_ENABLE;
689 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
691 /* clear lock enable and setup field */
692 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
693 value &= ~PLLE_MISC_LOCK_ENABLE;
694 value &= ~PLLE_MISC_SETUP_BASE(0xffff);
695 value &= ~PLLE_MISC_SETUP_EXT(0x3);
696 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
698 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
699 if ((value & PLLE_MISC_PLL_READY) == 0) {
700 err = tegra_plle_train();
702 pr_err("failed to train PLLE: %d", err);
707 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
708 value |= PLLE_MISC_SETUP_BASE(0x7);
709 value |= PLLE_MISC_LOCK_ENABLE;
710 value |= PLLE_MISC_SETUP_EXT(0);
711 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
713 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
714 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
715 PLLE_SS_CNTL_BYPASS_SS;
716 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
718 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
719 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
720 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
723 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
724 if (value & PLLE_MISC_LOCK)
731 pr_err("timeout waiting for PLLE to lock");
737 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
738 value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
739 value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
741 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
742 value |= PLLE_SS_CNTL_SSCINC(0x01);
744 value &= ~PLLE_SS_CNTL_SSCBYP;
745 value &= ~PLLE_SS_CNTL_INTERP_RESET;
746 value &= ~PLLE_SS_CNTL_BYPASS_SS;
748 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
749 value |= PLLE_SS_CNTL_SSCMAX(0x24);
750 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
755 struct periph_clk_init periph_clk_init_table[] = {
756 { PERIPH_ID_SPI1, CLOCK_ID_PERIPH },
757 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
758 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
759 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
760 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
761 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
762 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
763 { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
764 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
765 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
766 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
767 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
768 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
769 { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
770 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
771 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
772 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },