arch/arm/mach-tegra/tegra124/xusb-padctl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
   7
   8 #include <common.h>
   9 #include <errno.h>
  10 #include <log.h>
  11 #include <dm/of_access.h>
  12 #include <dm/ofnode.h>
  13 #include <linux/delay.h>
  14
  15 #include "../xusb-padctl-common.h"
  16
  17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  18
  19 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
  20 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
  21 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
  22 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
  23
  24 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
  25 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
  26 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
  27 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
  28
  29 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
  30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
  31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
  32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
  33
  34 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
  35 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
  36 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
  37 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
  38 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
  39 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
  40
  41 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
  42 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
  43 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
  44
  45 enum tegra124_function {
  46         TEGRA124_FUNC_SNPS,
  47         TEGRA124_FUNC_XUSB,
  48         TEGRA124_FUNC_UART,
  49         TEGRA124_FUNC_PCIE,
  50         TEGRA124_FUNC_USB3,
  51         TEGRA124_FUNC_SATA,
  52         TEGRA124_FUNC_RSVD,
  53 };
  54
  55 static const char *const tegra124_functions[] = {
  56         "snps",
  57         "xusb",
  58         "uart",
  59         "pcie",
  60         "usb3",
  61         "sata",
  62         "rsvd",
  63 };
  64
  65 static const unsigned int tegra124_otg_functions[] = {
  66         TEGRA124_FUNC_SNPS,
  67         TEGRA124_FUNC_XUSB,
  68         TEGRA124_FUNC_UART,
  69         TEGRA124_FUNC_RSVD,
  70 };
  71
  72 static const unsigned int tegra124_usb_functions[] = {
  73         TEGRA124_FUNC_SNPS,
  74         TEGRA124_FUNC_XUSB,
  75 };
  76
  77 static const unsigned int tegra124_pci_functions[] = {
  78         TEGRA124_FUNC_PCIE,
  79         TEGRA124_FUNC_USB3,
  80         TEGRA124_FUNC_SATA,
  81         TEGRA124_FUNC_RSVD,
  82 };
  83
  84 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)     \
  85         {                                                               \
  86                 .name = _name,                                          \
  87                 .offset = _offset,                                      \
  88                 .shift = _shift,                                        \
  89                 .mask = _mask,                                          \
  90                 .iddq = _iddq,                                          \
  91                 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
  92                 .funcs = tegra124_##_funcs##_functions,                 \
  93         }
  94
  95 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
  96         TEGRA124_LANE("otg-0",  0x004,  0, 0x3, 0, otg),
  97         TEGRA124_LANE("otg-1",  0x004,  2, 0x3, 0, otg),
  98         TEGRA124_LANE("otg-2",  0x004,  4, 0x3, 0, otg),
  99         TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
 100         TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
 101         TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
 102         TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
 103         TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
 104         TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
 105         TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
 106         TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
 107         TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
 108 };
 109
 110 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
 111 {
 112         u32 value;
 113
 114         if (padctl->enable++ > 0)
 115                 return 0;
 116
 117         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 118         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
 119         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 120
 121         udelay(100);
 122
 123         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 124         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
 125         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 126
 127         udelay(100);
 128
 129         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 130         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
 131         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 132
 133         return 0;
 134 }
 135
 136 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
 137 {
 138         u32 value;
 139
 140         if (padctl->enable == 0) {
 141                 pr_err("unbalanced enable/disable");
 142                 return 0;
 143         }
 144
 145         if (--padctl->enable > 0)
 146                 return 0;
 147
 148         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 149         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
 150         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 151
 152         udelay(100);
 153
 154         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 155         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
 156         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 157
 158         udelay(100);
 159
 160         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 161         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
 162         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 163
 164         return 0;
 165 }
 166
 167 static int phy_prepare(struct tegra_xusb_phy *phy)
 168 {
 169         return tegra_xusb_padctl_enable(phy->padctl);
 170 }
 171
 172 static int phy_unprepare(struct tegra_xusb_phy *phy)
 173 {
 174         return tegra_xusb_padctl_disable(phy->padctl);
 175 }
 176
 177 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
 178 {
 179         struct tegra_xusb_padctl *padctl = phy->padctl;
 180         int err = -ETIMEDOUT;
 181         unsigned long start;
 182         u32 value;
 183
 184         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 185         value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
 186         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 187
 188         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
 189         value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
 190                  XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
 191                  XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
 192         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
 193
 194         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 195         value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
 196         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 197
 198         start = get_timer(0);
 199
 200         while (get_timer(start) < 50) {
 201                 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 202                 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
 203                         err = 0;
 204                         break;
 205                 }
 206         }
 207
 208         return err;
 209 }
 210
 211 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
 212 {
 213         struct tegra_xusb_padctl *padctl = phy->padctl;
 214         u32 value;
 215
 216         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 217         value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
 218         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 219
 220         return 0;
 221 }
 222
 223 static int sata_phy_enable(struct tegra_xusb_phy *phy)
 224 {
 225         struct tegra_xusb_padctl *padctl = phy->padctl;
 226         int err = -ETIMEDOUT;
 227         unsigned long start;
 228         u32 value;
 229
 230         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
 231         value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
 232         value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
 233         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
 234
 235         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 236         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
 237         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
 238         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 239
 240         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 241         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
 242         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 243
 244         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 245         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
 246         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 247
 248         start = get_timer(0);
 249
 250         while (get_timer(start) < 50) {
 251                 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 252                 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
 253                         err = 0;
 254                         break;
 255                 }
 256         }
 257
 258         return err;
 259 }
 260
 261 static int sata_phy_disable(struct tegra_xusb_phy *phy)
 262 {
 263         struct tegra_xusb_padctl *padctl = phy->padctl;
 264         u32 value;
 265
 266         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 267         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
 268         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 269
 270         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 271         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
 272         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 273
 274         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 275         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
 276         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
 277         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 278
 279         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
 280         value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
 281         value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
 282         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
 283
 284         return 0;
 285 }
 286
 287 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
 288         .prepare = phy_prepare,
 289         .enable = pcie_phy_enable,
 290         .disable = pcie_phy_disable,
 291         .unprepare = phy_unprepare,
 292 };
 293
 294 static const struct tegra_xusb_phy_ops sata_phy_ops = {
 295         .prepare = phy_prepare,
 296         .enable = sata_phy_enable,
 297         .disable = sata_phy_disable,
 298         .unprepare = phy_unprepare,
 299 };
 300
 301 static struct tegra_xusb_phy tegra124_phys[] = {
 302         {
 303                 .type = TEGRA_XUSB_PADCTL_PCIE,
 304                 .ops = &pcie_phy_ops,
 305                 .padctl = &padctl,
 306         },
 307         {
 308                 .type = TEGRA_XUSB_PADCTL_SATA,
 309                 .ops = &sata_phy_ops,
 310                 .padctl = &padctl,
 311         },
 312 };
 313
 314 static const struct tegra_xusb_padctl_soc tegra124_socdata = {
 315         .lanes = tegra124_lanes,
 316         .num_lanes = ARRAY_SIZE(tegra124_lanes),
 317         .functions = tegra124_functions,
 318         .num_functions = ARRAY_SIZE(tegra124_functions),
 319         .phys = tegra124_phys,
 320         .num_phys = ARRAY_SIZE(tegra124_phys),
 321 };
 322
 323 void tegra_xusb_padctl_init(void)
 324 {
 325         ofnode nodes[1];
 326         int count = 0;
 327         int ret;
 328
 329         debug("%s: start\n", __func__);
 330         if (of_live_active()) {
 331                 struct device_node *np = of_find_compatible_node(NULL, NULL,
 332                                                 "nvidia,tegra124-xusb-padctl");
 333
 334                 debug("np=%p\n", np);
 335                 if (np) {
 336                         nodes[0] = np_to_ofnode(np);
 337                         count = 1;
 338                 }
 339         } else {
 340                 int node_offsets[1];
 341                 int i;
 342
 343                 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
 344                                 COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
 345                                 node_offsets, ARRAY_SIZE(node_offsets));
 346                 for (i = 0; i < count; i++)
 347                         nodes[i] = offset_to_ofnode(node_offsets[i]);
 348         }
 349
 350         ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata);
 351         debug("%s: done, ret=%d\n", __func__, ret);
 352 }