arch/arm/mach-sunxi/spl_spi_sunxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <spl.h>
   8 #include <asm/gpio.h>
   9 #include <asm/io.h>
  10 #include <linux/libfdt.h>
  11
  12 #ifdef CONFIG_SPL_OS_BOOT
  13 #error CONFIG_SPL_OS_BOOT is not supported yet
  14 #endif
  15
  16 /*
  17  * This is a very simple U-Boot image loading implementation, trying to
  18  * replicate what the boot ROM is doing when loading the SPL. Because we
  19  * know the exact pins where the SPI Flash is connected and also know
  20  * that the Read Data Bytes (03h) command is supported, the hardware
  21  * configuration is very simple and we don't need the extra flexibility
  22  * of the SPI framework. Moreover, we rely on the default settings of
  23  * the SPI controler hardware registers and only adjust what needs to
  24  * be changed. This is good for the code size and this implementation
  25  * adds less than 400 bytes to the SPL.
  26  *
  27  * There are two variants of the SPI controller in Allwinner SoCs:
  28  * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
  29  * Both of them are supported.
  30  *
  31  * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
  32  * supported at the moment.
  33  */
  34
  35 /*****************************************************************************/
  36 /* SUN4I variant of the SPI controller                                       */
  37 /*****************************************************************************/
  38
  39 #define SUN4I_SPI0_CCTL             0x1C
  40 #define SUN4I_SPI0_CTL              0x08
  41 #define SUN4I_SPI0_RX               0x00
  42 #define SUN4I_SPI0_TX               0x04
  43 #define SUN4I_SPI0_FIFO_STA         0x28
  44 #define SUN4I_SPI0_BC               0x20
  45 #define SUN4I_SPI0_TC               0x24
  46
  47 #define SUN4I_CTL_ENABLE            BIT(0)
  48 #define SUN4I_CTL_MASTER            BIT(1)
  49 #define SUN4I_CTL_TF_RST            BIT(8)
  50 #define SUN4I_CTL_RF_RST            BIT(9)
  51 #define SUN4I_CTL_XCH               BIT(10)
  52
  53 /*****************************************************************************/
  54 /* SUN6I variant of the SPI controller                                       */
  55 /*****************************************************************************/
  56
  57 #define SUN6I_SPI0_CCTL             0x24
  58 #define SUN6I_SPI0_GCR              0x04
  59 #define SUN6I_SPI0_TCR              0x08
  60 #define SUN6I_SPI0_FIFO_STA         0x1C
  61 #define SUN6I_SPI0_MBC              0x30
  62 #define SUN6I_SPI0_MTC              0x34
  63 #define SUN6I_SPI0_BCC              0x38
  64 #define SUN6I_SPI0_TXD              0x200
  65 #define SUN6I_SPI0_RXD              0x300
  66
  67 #define SUN6I_CTL_ENABLE            BIT(0)
  68 #define SUN6I_CTL_MASTER            BIT(1)
  69 #define SUN6I_CTL_SRST              BIT(31)
  70 #define SUN6I_TCR_XCH               BIT(31)
  71
  72 /*****************************************************************************/
  73
  74 #define CCM_AHB_GATING0             (0x01C20000 + 0x60)
  75 #define CCM_SPI0_CLK                (0x01C20000 + 0xA0)
  76 #define SUN6I_BUS_SOFT_RST_REG0     (0x01C20000 + 0x2C0)
  77
  78 #define AHB_RESET_SPI0_SHIFT        20
  79 #define AHB_GATE_OFFSET_SPI0        20
  80
  81 #define SPI0_CLK_DIV_BY_2           0x1000
  82 #define SPI0_CLK_DIV_BY_4           0x1001
  83
  84 /*****************************************************************************/
  85
  86 /*
  87  * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
  88  * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
  89  */
  90 static void spi0_pinmux_setup(unsigned int pin_function)
  91 {
  92         unsigned int pin;
  93
  94         for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
  95                 sunxi_gpio_set_cfgpin(pin, pin_function);
  96
  97         if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
  98                 sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
  99         else
 100                 sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
 101 }
 102
 103 static bool is_sun6i_gen_spi(void)
 104 {
 105         return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I);
 106 }
 107
 108 static uintptr_t spi0_base_address(void)
 109 {
 110         if (!is_sun6i_gen_spi())
 111                 return 0x01C05000;
 112
 113         return 0x01C68000;
 114 }
 115
 116 /*
 117  * Setup 6 MHz from OSC24M (because the BROM is doing the same).
 118  */
 119 static void spi0_enable_clock(void)
 120 {
 121         uintptr_t base = spi0_base_address();
 122
 123         /* Deassert SPI0 reset on SUN6I */
 124         if (is_sun6i_gen_spi())
 125                 setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 126                              (1 << AHB_RESET_SPI0_SHIFT));
 127
 128         /* Open the SPI0 gate */
 129         setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 130
 131         /* Divide by 4 */
 132         writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
 133                                   SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
 134         /* 24MHz from OSC24M */
 135         writel((1 << 31), CCM_SPI0_CLK);
 136
 137         if (is_sun6i_gen_spi()) {
 138                 /* Enable SPI in the master mode and do a soft reset */
 139                 setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 140                              SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
 141                 /* Wait for completion */
 142                 while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
 143                         ;
 144         } else {
 145                 /* Enable SPI in the master mode and reset FIFO */
 146                 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 147                                                     SUN4I_CTL_ENABLE |
 148                                                     SUN4I_CTL_TF_RST |
 149                                                     SUN4I_CTL_RF_RST);
 150         }
 151 }
 152
 153 static void spi0_disable_clock(void)
 154 {
 155         uintptr_t base = spi0_base_address();
 156
 157         /* Disable the SPI0 controller */
 158         if (is_sun6i_gen_spi())
 159                 clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 160                                              SUN6I_CTL_ENABLE);
 161         else
 162                 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 163                                              SUN4I_CTL_ENABLE);
 164
 165         /* Disable the SPI0 clock */
 166         writel(0, CCM_SPI0_CLK);
 167
 168         /* Close the SPI0 gate */
 169         clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 170
 171         /* Assert SPI0 reset on SUN6I */
 172         if (is_sun6i_gen_spi())
 173                 clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 174                              (1 << AHB_RESET_SPI0_SHIFT));
 175 }
 176
 177 static void spi0_init(void)
 178 {
 179         unsigned int pin_function = SUNXI_GPC_SPI0;
 180
 181         if (IS_ENABLED(CONFIG_MACH_SUN50I))
 182                 pin_function = SUN50I_GPC_SPI0;
 183
 184         spi0_pinmux_setup(pin_function);
 185         spi0_enable_clock();
 186 }
 187
 188 static void spi0_deinit(void)
 189 {
 190         /* New SoCs can disable pins, older could only set them as input */
 191         unsigned int pin_function = SUNXI_GPIO_INPUT;
 192
 193         if (is_sun6i_gen_spi())
 194                 pin_function = SUNXI_GPIO_DISABLE;
 195
 196         spi0_disable_clock();
 197         spi0_pinmux_setup(pin_function);
 198 }
 199
 200 /*****************************************************************************/
 201
 202 #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
 203
 204 static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
 205                                  ulong spi_ctl_reg,
 206                                  ulong spi_ctl_xch_bitmask,
 207                                  ulong spi_fifo_reg,
 208                                  ulong spi_tx_reg,
 209                                  ulong spi_rx_reg,
 210                                  ulong spi_bc_reg,
 211                                  ulong spi_tc_reg,
 212                                  ulong spi_bcc_reg)
 213 {
 214         writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
 215         writel(4, spi_tc_reg);           /* Transfer counter (bytes to send) */
 216         if (spi_bcc_reg)
 217                 writel(4, spi_bcc_reg);  /* SUN6I also needs this */
 218
 219         /* Send the Read Data Bytes (03h) command header */
 220         writeb(0x03, spi_tx_reg);
 221         writeb((u8)(addr >> 16), spi_tx_reg);
 222         writeb((u8)(addr >> 8), spi_tx_reg);
 223         writeb((u8)(addr), spi_tx_reg);
 224
 225         /* Start the data transfer */
 226         setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
 227
 228         /* Wait until everything is received in the RX FIFO */
 229         while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
 230                 ;
 231
 232         /* Skip 4 bytes */
 233         readl(spi_rx_reg);
 234
 235         /* Read the data */
 236         while (bufsize-- > 0)
 237                 *buf++ = readb(spi_rx_reg);
 238
 239         /* tSHSL time is up to 100 ns in various SPI flash datasheets */
 240         udelay(1);
 241 }
 242
 243 static void spi0_read_data(void *buf, u32 addr, u32 len)
 244 {
 245         u8 *buf8 = buf;
 246         u32 chunk_len;
 247         uintptr_t base = spi0_base_address();
 248
 249         while (len > 0) {
 250                 chunk_len = len;
 251                 if (chunk_len > SPI_READ_MAX_SIZE)
 252                         chunk_len = SPI_READ_MAX_SIZE;
 253
 254                 if (is_sun6i_gen_spi()) {
 255                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 256                                              base + SUN6I_SPI0_TCR,
 257                                              SUN6I_TCR_XCH,
 258                                              base + SUN6I_SPI0_FIFO_STA,
 259                                              base + SUN6I_SPI0_TXD,
 260                                              base + SUN6I_SPI0_RXD,
 261                                              base + SUN6I_SPI0_MBC,
 262                                              base + SUN6I_SPI0_MTC,
 263                                              base + SUN6I_SPI0_BCC);
 264                 } else {
 265                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 266                                              base + SUN4I_SPI0_CTL,
 267                                              SUN4I_CTL_XCH,
 268                                              base + SUN4I_SPI0_FIFO_STA,
 269                                              base + SUN4I_SPI0_TX,
 270                                              base + SUN4I_SPI0_RX,
 271                                              base + SUN4I_SPI0_BC,
 272                                              base + SUN4I_SPI0_TC,
 273                                              0);
 274                 }
 275
 276                 len  -= chunk_len;
 277                 buf8 += chunk_len;
 278                 addr += chunk_len;
 279         }
 280 }
 281
 282 static ulong spi_load_read(struct spl_load_info *load, ulong sector,
 283                            ulong count, void *buf)
 284 {
 285         spi0_read_data(buf, sector, count);
 286
 287         return count;
 288 }
 289
 290 /*****************************************************************************/
 291
 292 static int spl_spi_load_image(struct spl_image_info *spl_image,
 293                               struct spl_boot_device *bootdev)
 294 {
 295         int ret = 0;
 296         struct image_header *header;
 297         header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
 298
 299         spi0_init();
 300
 301         spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
 302
 303         if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
 304                 image_get_magic(header) == FDT_MAGIC) {
 305                 struct spl_load_info load;
 306
 307                 debug("Found FIT image\n");
 308                 load.dev = NULL;
 309                 load.priv = NULL;
 310                 load.filename = NULL;
 311                 load.bl_len = 1;
 312                 load.read = spi_load_read;
 313                 ret = spl_load_simple_fit(spl_image, &load,
 314                                           CONFIG_SYS_SPI_U_BOOT_OFFS, header);
 315         } else {
 316                 ret = spl_parse_image_header(spl_image, header);
 317                 if (ret)
 318                         return ret;
 319
 320                 spi0_read_data((void *)spl_image->load_addr,
 321                                CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size);
 322         }
 323
 324         spi0_deinit();
 325
 326         return ret;
 327 }
 328 /* Use priorty 0 to override the default if it happens to be linked in */
 329 SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);