arch/arm/mach-sunxi/spl_spi_sunxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <image.h>
   8 #include <log.h>
   9 #include <spl.h>
  10 #include <asm/gpio.h>
  11 #include <asm/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/libfdt.h>
  14
  15 #ifdef CONFIG_SPL_OS_BOOT
  16 #error CONFIG_SPL_OS_BOOT is not supported yet
  17 #endif
  18
  19 /*
  20  * This is a very simple U-Boot image loading implementation, trying to
  21  * replicate what the boot ROM is doing when loading the SPL. Because we
  22  * know the exact pins where the SPI Flash is connected and also know
  23  * that the Read Data Bytes (03h) command is supported, the hardware
  24  * configuration is very simple and we don't need the extra flexibility
  25  * of the SPI framework. Moreover, we rely on the default settings of
  26  * the SPI controler hardware registers and only adjust what needs to
  27  * be changed. This is good for the code size and this implementation
  28  * adds less than 400 bytes to the SPL.
  29  *
  30  * There are two variants of the SPI controller in Allwinner SoCs:
  31  * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
  32  * Both of them are supported.
  33  *
  34  * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
  35  * supported at the moment.
  36  */
  37
  38 /*****************************************************************************/
  39 /* SUN4I variant of the SPI controller                                       */
  40 /*****************************************************************************/
  41
  42 #define SUN4I_SPI0_CCTL             0x1C
  43 #define SUN4I_SPI0_CTL              0x08
  44 #define SUN4I_SPI0_RX               0x00
  45 #define SUN4I_SPI0_TX               0x04
  46 #define SUN4I_SPI0_FIFO_STA         0x28
  47 #define SUN4I_SPI0_BC               0x20
  48 #define SUN4I_SPI0_TC               0x24
  49
  50 #define SUN4I_CTL_ENABLE            BIT(0)
  51 #define SUN4I_CTL_MASTER            BIT(1)
  52 #define SUN4I_CTL_TF_RST            BIT(8)
  53 #define SUN4I_CTL_RF_RST            BIT(9)
  54 #define SUN4I_CTL_XCH               BIT(10)
  55
  56 /*****************************************************************************/
  57 /* SUN6I variant of the SPI controller                                       */
  58 /*****************************************************************************/
  59
  60 #define SUN6I_SPI0_CCTL             0x24
  61 #define SUN6I_SPI0_GCR              0x04
  62 #define SUN6I_SPI0_TCR              0x08
  63 #define SUN6I_SPI0_FIFO_STA         0x1C
  64 #define SUN6I_SPI0_MBC              0x30
  65 #define SUN6I_SPI0_MTC              0x34
  66 #define SUN6I_SPI0_BCC              0x38
  67 #define SUN6I_SPI0_TXD              0x200
  68 #define SUN6I_SPI0_RXD              0x300
  69
  70 #define SUN6I_CTL_ENABLE            BIT(0)
  71 #define SUN6I_CTL_MASTER            BIT(1)
  72 #define SUN6I_CTL_SRST              BIT(31)
  73 #define SUN6I_TCR_XCH               BIT(31)
  74
  75 /*****************************************************************************/
  76
  77 #define CCM_AHB_GATING0             (0x01C20000 + 0x60)
  78 #define CCM_H6_SPI_BGR_REG          (0x03001000 + 0x96c)
  79 #ifdef CONFIG_MACH_SUN50I_H6
  80 #define CCM_SPI0_CLK                (0x03001000 + 0x940)
  81 #else
  82 #define CCM_SPI0_CLK                (0x01C20000 + 0xA0)
  83 #endif
  84 #define SUN6I_BUS_SOFT_RST_REG0     (0x01C20000 + 0x2C0)
  85
  86 #define AHB_RESET_SPI0_SHIFT        20
  87 #define AHB_GATE_OFFSET_SPI0        20
  88
  89 #define SPI0_CLK_DIV_BY_2           0x1000
  90 #define SPI0_CLK_DIV_BY_4           0x1001
  91
  92 /*****************************************************************************/
  93
  94 /*
  95  * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
  96  * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
  97  * The H6 uses PC0, PC2, PC3, PC5.
  98  */
  99 static void spi0_pinmux_setup(unsigned int pin_function)
 100 {
 101         /* All chips use PC0 and PC2. */
 102         sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
 103         sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
 104
 105         /* All chips except H6 use PC1, and only H6 uses PC5. */
 106         if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 107                 sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
 108         else
 109                 sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
 110
 111         /* Older generations use PC23 for CS, newer ones use PC3. */
 112         if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
 113             IS_ENABLED(CONFIG_MACH_SUN8I_R40))
 114                 sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
 115         else
 116                 sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
 117 }
 118
 119 static bool is_sun6i_gen_spi(void)
 120 {
 121         return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
 122                IS_ENABLED(CONFIG_MACH_SUN50I_H6);
 123 }
 124
 125 static uintptr_t spi0_base_address(void)
 126 {
 127         if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
 128                 return 0x01C05000;
 129
 130         if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 131                 return 0x05010000;
 132
 133         if (!is_sun6i_gen_spi())
 134                 return 0x01C05000;
 135
 136         return 0x01C68000;
 137 }
 138
 139 /*
 140  * Setup 6 MHz from OSC24M (because the BROM is doing the same).
 141  */
 142 static void spi0_enable_clock(void)
 143 {
 144         uintptr_t base = spi0_base_address();
 145
 146         /* Deassert SPI0 reset on SUN6I */
 147         if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 148                 setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
 149         else if (is_sun6i_gen_spi())
 150                 setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 151                              (1 << AHB_RESET_SPI0_SHIFT));
 152
 153         /* Open the SPI0 gate */
 154         if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 155                 setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 156
 157         /* Divide by 4 */
 158         writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
 159                                   SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
 160         /* 24MHz from OSC24M */
 161         writel((1 << 31), CCM_SPI0_CLK);
 162
 163         if (is_sun6i_gen_spi()) {
 164                 /* Enable SPI in the master mode and do a soft reset */
 165                 setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 166                              SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
 167                 /* Wait for completion */
 168                 while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
 169                         ;
 170         } else {
 171                 /* Enable SPI in the master mode and reset FIFO */
 172                 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 173                                                     SUN4I_CTL_ENABLE |
 174                                                     SUN4I_CTL_TF_RST |
 175                                                     SUN4I_CTL_RF_RST);
 176         }
 177 }
 178
 179 static void spi0_disable_clock(void)
 180 {
 181         uintptr_t base = spi0_base_address();
 182
 183         /* Disable the SPI0 controller */
 184         if (is_sun6i_gen_spi())
 185                 clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 186                                              SUN6I_CTL_ENABLE);
 187         else
 188                 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 189                                              SUN4I_CTL_ENABLE);
 190
 191         /* Disable the SPI0 clock */
 192         writel(0, CCM_SPI0_CLK);
 193
 194         /* Close the SPI0 gate */
 195         if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 196                 clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 197
 198         /* Assert SPI0 reset on SUN6I */
 199         if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 200                 clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
 201         else if (is_sun6i_gen_spi())
 202                 clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 203                              (1 << AHB_RESET_SPI0_SHIFT));
 204 }
 205
 206 static void spi0_init(void)
 207 {
 208         unsigned int pin_function = SUNXI_GPC_SPI0;
 209
 210         if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
 211             IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 212                 pin_function = SUN50I_GPC_SPI0;
 213
 214         spi0_pinmux_setup(pin_function);
 215         spi0_enable_clock();
 216 }
 217
 218 static void spi0_deinit(void)
 219 {
 220         /* New SoCs can disable pins, older could only set them as input */
 221         unsigned int pin_function = SUNXI_GPIO_INPUT;
 222
 223         if (is_sun6i_gen_spi())
 224                 pin_function = SUNXI_GPIO_DISABLE;
 225
 226         spi0_disable_clock();
 227         spi0_pinmux_setup(pin_function);
 228 }
 229
 230 /*****************************************************************************/
 231
 232 #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
 233
 234 static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
 235                                  ulong spi_ctl_reg,
 236                                  ulong spi_ctl_xch_bitmask,
 237                                  ulong spi_fifo_reg,
 238                                  ulong spi_tx_reg,
 239                                  ulong spi_rx_reg,
 240                                  ulong spi_bc_reg,
 241                                  ulong spi_tc_reg,
 242                                  ulong spi_bcc_reg)
 243 {
 244         writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
 245         writel(4, spi_tc_reg);           /* Transfer counter (bytes to send) */
 246         if (spi_bcc_reg)
 247                 writel(4, spi_bcc_reg);  /* SUN6I also needs this */
 248
 249         /* Send the Read Data Bytes (03h) command header */
 250         writeb(0x03, spi_tx_reg);
 251         writeb((u8)(addr >> 16), spi_tx_reg);
 252         writeb((u8)(addr >> 8), spi_tx_reg);
 253         writeb((u8)(addr), spi_tx_reg);
 254
 255         /* Start the data transfer */
 256         setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
 257
 258         /* Wait until everything is received in the RX FIFO */
 259         while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
 260                 ;
 261
 262         /* Skip 4 bytes */
 263         readl(spi_rx_reg);
 264
 265         /* Read the data */
 266         while (bufsize-- > 0)
 267                 *buf++ = readb(spi_rx_reg);
 268
 269         /* tSHSL time is up to 100 ns in various SPI flash datasheets */
 270         udelay(1);
 271 }
 272
 273 static void spi0_read_data(void *buf, u32 addr, u32 len)
 274 {
 275         u8 *buf8 = buf;
 276         u32 chunk_len;
 277         uintptr_t base = spi0_base_address();
 278
 279         while (len > 0) {
 280                 chunk_len = len;
 281                 if (chunk_len > SPI_READ_MAX_SIZE)
 282                         chunk_len = SPI_READ_MAX_SIZE;
 283
 284                 if (is_sun6i_gen_spi()) {
 285                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 286                                              base + SUN6I_SPI0_TCR,
 287                                              SUN6I_TCR_XCH,
 288                                              base + SUN6I_SPI0_FIFO_STA,
 289                                              base + SUN6I_SPI0_TXD,
 290                                              base + SUN6I_SPI0_RXD,
 291                                              base + SUN6I_SPI0_MBC,
 292                                              base + SUN6I_SPI0_MTC,
 293                                              base + SUN6I_SPI0_BCC);
 294                 } else {
 295                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 296                                              base + SUN4I_SPI0_CTL,
 297                                              SUN4I_CTL_XCH,
 298                                              base + SUN4I_SPI0_FIFO_STA,
 299                                              base + SUN4I_SPI0_TX,
 300                                              base + SUN4I_SPI0_RX,
 301                                              base + SUN4I_SPI0_BC,
 302                                              base + SUN4I_SPI0_TC,
 303                                              0);
 304                 }
 305
 306                 len  -= chunk_len;
 307                 buf8 += chunk_len;
 308                 addr += chunk_len;
 309         }
 310 }
 311
 312 static ulong spi_load_read(struct spl_load_info *load, ulong sector,
 313                            ulong count, void *buf)
 314 {
 315         spi0_read_data(buf, sector, count);
 316
 317         return count;
 318 }
 319
 320 /*****************************************************************************/
 321
 322 static int spl_spi_load_image(struct spl_image_info *spl_image,
 323                               struct spl_boot_device *bootdev)
 324 {
 325         int ret = 0;
 326         struct image_header *header;
 327         header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
 328
 329         spi0_init();
 330
 331         spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
 332
 333         if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
 334                 image_get_magic(header) == FDT_MAGIC) {
 335                 struct spl_load_info load;
 336
 337                 debug("Found FIT image\n");
 338                 load.dev = NULL;
 339                 load.priv = NULL;
 340                 load.filename = NULL;
 341                 load.bl_len = 1;
 342                 load.read = spi_load_read;
 343                 ret = spl_load_simple_fit(spl_image, &load,
 344                                           CONFIG_SYS_SPI_U_BOOT_OFFS, header);
 345         } else {
 346                 ret = spl_parse_image_header(spl_image, header);
 347                 if (ret)
 348                         return ret;
 349
 350                 spi0_read_data((void *)spl_image->load_addr,
 351                                CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size);
 352         }
 353
 354         spi0_deinit();
 355
 356         return ret;
 357 }
 358 /* Use priorty 0 to override the default if it happens to be linked in */
 359 SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);