arch/arm/mach-sunxi/dram_sun8i_a83t.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Sun8i a33 platform dram controller init.
   4  *
   5  * (C) Copyright 2007-2015 Allwinner Technology Co.
   6  *                         Jerry Wang <wangflord@allwinnertech.com>
   7  * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
   8  * (C) Copyright 2015      Hans de Goede <hdegoede@redhat.com>
   9  */
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/dram.h>
  15 #include <asm/arch/prcm.h>
  16
  17 #define DRAM_CLK_MUL 2
  18 #define DRAM_CLK_DIV 1
  19
  20 struct dram_para {
  21         u8 cs1;
  22         u8 seq;
  23         u8 bank;
  24         u8 rank;
  25         u8 rows;
  26         u8 bus_width;
  27         u8 dram_type;
  28         u16 page_size;
  29 };
  30
  31 static void mctl_set_cr(struct dram_para *para)
  32 {
  33         struct sunxi_mctl_com_reg * const mctl_com =
  34                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  35
  36         writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
  37                 MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) |
  38                 (para->seq ? MCTL_CR_SEQUENCE : 0) |
  39                 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
  40                 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
  41                 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
  42                 &mctl_com->cr);
  43 }
  44
  45 static void auto_detect_dram_size(struct dram_para *para)
  46 {
  47         u8 orig_rank = para->rank;
  48         int rows, columns;
  49
  50         /* Row detect */
  51         para->page_size = 512;
  52         para->seq = 1;
  53         para->rows = 16;
  54         para->rank = 1;
  55         mctl_set_cr(para);
  56         for (rows = 11 ; rows < 16 ; rows++) {
  57                 if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
  58                         break;
  59         }
  60
  61         /* Column (page size) detect */
  62         para->rows = 11;
  63         para->page_size = 8192;
  64         mctl_set_cr(para);
  65         for (columns = 9 ; columns < 13 ; columns++) {
  66                 if (mctl_mem_matches(1 << columns))
  67                         break;
  68         }
  69
  70         para->seq = 0;
  71         para->rank = orig_rank;
  72         para->rows = rows;
  73         para->page_size = 1 << columns;
  74         mctl_set_cr(para);
  75 }
  76
  77 static inline int ns_to_t(int nanoseconds)
  78 {
  79         const unsigned int ctrl_freq =
  80                 CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
  81
  82         return (ctrl_freq * nanoseconds + 999) / 1000;
  83 }
  84
  85 static void auto_set_timing_para(struct dram_para *para)
  86 {
  87         struct sunxi_mctl_ctl_reg * const mctl_ctl =
  88                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  89
  90         u32 reg_val;
  91
  92         u8 tccd         = 2;
  93         u8 tfaw         = ns_to_t(50);
  94         u8 trrd         = max(ns_to_t(10), 4);
  95         u8 trcd         = ns_to_t(15);
  96         u8 trc          = ns_to_t(53);
  97         u8 txp          = max(ns_to_t(8), 3);
  98         u8 twtr         = max(ns_to_t(8), 4);
  99         u8 trtp         = max(ns_to_t(8), 4);
 100         u8 twr          = max(ns_to_t(15), 3);
 101         u8 trp          = ns_to_t(15);
 102         u8 tras         = ns_to_t(38);
 103
 104         u16 trefi       = ns_to_t(7800) / 32;
 105         u16 trfc        = ns_to_t(350);
 106
 107         /* Fixed timing parameters */
 108         u8 tmrw         = 0;
 109         u8 tmrd         = 4;
 110         u8 tmod         = 12;
 111         u8 tcke         = 3;
 112         u8 tcksrx       = 5;
 113         u8 tcksre       = 5;
 114         u8 tckesr       = 4;
 115         u8 trasmax      = 24;
 116         u8 tcl          = 6; /* CL 12 */
 117         u8 tcwl         = 4; /* CWL 8 */
 118         u8 t_rdata_en   = 4;
 119         u8 wr_latency   = 2;
 120
 121         u32 tdinit0     = (500 * CONFIG_DRAM_CLK) + 1;          /* 500us */
 122         u32 tdinit1     = (360 * CONFIG_DRAM_CLK) / 1000 + 1;   /* 360ns */
 123         u32 tdinit2     = (200 * CONFIG_DRAM_CLK) + 1;          /* 200us */
 124         u32 tdinit3     = (1 * CONFIG_DRAM_CLK) + 1;            /* 1us */
 125
 126         u8 twtp         = tcwl + 2 + twr;       /* WL + BL / 2 + tWR */
 127         u8 twr2rd       = tcwl + 2 + twtr;      /* WL + BL / 2 + tWTR */
 128         u8 trd2wr       = tcl + 2 + 1 - tcwl;   /* RL + BL / 2 + 2 - WL */
 129
 130         /* Set work mode register */
 131         mctl_set_cr(para);
 132         /* Set mode register */
 133         if (para->dram_type == DRAM_TYPE_DDR3) {
 134                 writel(MCTL_MR0, &mctl_ctl->mr0);
 135                 writel(MCTL_MR1, &mctl_ctl->mr1);
 136                 writel(MCTL_MR2, &mctl_ctl->mr2);
 137                 writel(MCTL_MR3, &mctl_ctl->mr3);
 138         } else if (para->dram_type == DRAM_TYPE_LPDDR3) {
 139                 writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0);
 140                 writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1);
 141                 writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2);
 142                 writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3);
 143
 144                 /* timing parameters for LPDDR3 */
 145                 tfaw = max(ns_to_t(50), 4);
 146                 trrd = max(ns_to_t(10), 2);
 147                 trcd = max(ns_to_t(24), 2);
 148                 trc = ns_to_t(70);
 149                 txp = max(ns_to_t(8), 2);
 150                 twtr = max(ns_to_t(8), 2);
 151                 trtp = max(ns_to_t(8), 2);
 152                 trp = max(ns_to_t(27), 2);
 153                 tras = ns_to_t(42);
 154                 trefi = ns_to_t(3900) / 32;
 155                 trfc = ns_to_t(210);
 156                 tmrw            = 5;
 157                 tmrd            = 5;
 158                 tckesr          = 5;
 159                 tcwl            = 3;    /* CWL 8 */
 160                 t_rdata_en      = 5;
 161                 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1;          /* 200us */
 162                 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1;   /* 100ns */
 163                 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1;   /* 200us */
 164                 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1;    /* 1us */
 165                 twtp    = tcwl + 4 + twr + 1;   /* CWL + BL/2 + tWR */
 166                 twr2rd  = tcwl + 4 + 1 + twtr;  /* WL + BL / 2 + tWTR */
 167                 trd2wr  = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */
 168         }
 169         /* Set dram timing */
 170         reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
 171         writel(reg_val, &mctl_ctl->dramtmg0);
 172         reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
 173         writel(reg_val, &mctl_ctl->dramtmg1);
 174         reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
 175         writel(reg_val, &mctl_ctl->dramtmg2);
 176         reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
 177         writel(reg_val, &mctl_ctl->dramtmg3);
 178         reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
 179         writel(reg_val, &mctl_ctl->dramtmg4);
 180         reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
 181         writel(reg_val, &mctl_ctl->dramtmg5);
 182         /* Set two rank timing and exit self-refresh timing */
 183         reg_val = readl(&mctl_ctl->dramtmg8);
 184         reg_val &= ~(0xff << 8);
 185         reg_val &= ~(0xff << 0);
 186         reg_val |= (0x33 << 8);
 187         reg_val |= (0x8 << 0);
 188         writel(reg_val, &mctl_ctl->dramtmg8);
 189         /* Set phy interface time */
 190         reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
 191                         | (wr_latency << 0);
 192         /* PHY interface write latency and read latency configure */
 193         writel(reg_val, &mctl_ctl->pitmg0);
 194         /* Set phy time  PTR0-2 use default */
 195         writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
 196         writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
 197         /* Set refresh timing */
 198         reg_val = (trefi << 16) | (trfc << 0);
 199         writel(reg_val, &mctl_ctl->rfshtmg);
 200 }
 201
 202 static void mctl_set_pir(u32 val)
 203 {
 204         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 205                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 206
 207         writel(val, &mctl_ctl->pir);
 208         mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
 209 }
 210
 211 static void mctl_data_train_cfg(struct dram_para *para)
 212 {
 213         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 214                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 215
 216         if (para->rank == 2)
 217                 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
 218         else
 219                 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
 220 }
 221
 222 static int mctl_train_dram(struct dram_para *para)
 223 {
 224         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 225                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 226
 227         mctl_data_train_cfg(para);
 228         mctl_set_pir(0x5f3);
 229
 230         return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
 231 }
 232
 233 static void set_master_priority(void)
 234 {
 235         writel(0x00a0000d, MCTL_MASTER_CFG0(0));
 236         writel(0x00500064, MCTL_MASTER_CFG1(0));
 237         writel(0x07000009, MCTL_MASTER_CFG0(1));
 238         writel(0x00000600, MCTL_MASTER_CFG1(1));
 239         writel(0x01000009, MCTL_MASTER_CFG0(3));
 240         writel(0x00000064, MCTL_MASTER_CFG1(3));
 241         writel(0x08000009, MCTL_MASTER_CFG0(4));
 242         writel(0x00000640, MCTL_MASTER_CFG1(4));
 243         writel(0x20000308, MCTL_MASTER_CFG0(8));
 244         writel(0x00001000, MCTL_MASTER_CFG1(8));
 245         writel(0x02800009, MCTL_MASTER_CFG0(9));
 246         writel(0x00000100, MCTL_MASTER_CFG1(9));
 247         writel(0x01800009, MCTL_MASTER_CFG0(5));
 248         writel(0x00000100, MCTL_MASTER_CFG1(5));
 249         writel(0x01800009, MCTL_MASTER_CFG0(7));
 250         writel(0x00000100, MCTL_MASTER_CFG1(7));
 251         writel(0x00640009, MCTL_MASTER_CFG0(6));
 252         writel(0x00000032, MCTL_MASTER_CFG1(6));
 253         writel(0x0100000d, MCTL_MASTER_CFG0(2));
 254         writel(0x00500080, MCTL_MASTER_CFG1(2));
 255 }
 256
 257 static int mctl_channel_init(struct dram_para *para)
 258 {
 259         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 260                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 261         struct sunxi_mctl_com_reg * const mctl_com =
 262                 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 263         u32 low_data_lines_status;  /* Training status of datalines 0 - 7 */
 264         u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
 265         u32 i, rval;
 266
 267         auto_set_timing_para(para);
 268
 269         /* Set dram master access priority */
 270         writel(0x000101a0, &mctl_com->bwcr);
 271         /* set cpu high priority */
 272         writel(0x1, &mctl_com->mapr);
 273         set_master_priority();
 274         udelay(250);
 275
 276         /* Disable dram VTC */
 277         clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30);
 278         clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26);
 279
 280         writel(0x94be6fa3, MCTL_PROTECT);
 281         udelay(100);
 282         clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16);
 283         writel(0x0, MCTL_PROTECT);
 284         udelay(100);
 285
 286
 287         /* Set ODT */
 288         if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
 289                 rval = 0x0;
 290         else
 291                 rval = 0x2;
 292
 293         for (i = 0 ; i < 11 ; i++) {
 294                 clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16),
 295                                 rval << 24);
 296                 clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16),
 297                                 rval << 24);
 298                 clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16),
 299                                 rval << 24);
 300                 clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16),
 301                                 rval << 24);
 302         }
 303
 304         for (i = 0; i < 31; i++)
 305                 clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26);
 306
 307         /* set PLL configuration */
 308         if (CONFIG_DRAM_CLK >= 480)
 309                 setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19);
 310         else
 311                 setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19);
 312
 313         /* Auto detect dram config, set 2 rank and 16bit bus-width */
 314         para->cs1 = 0;
 315         para->rank = 2;
 316         para->bus_width = 16;
 317         mctl_set_cr(para);
 318
 319         /* Open DQS gating */
 320         clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
 321         clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
 322
 323         if (para->dram_type == DRAM_TYPE_LPDDR3)
 324                 clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) ,
 325                                 0x1 << 31);
 326         if (readl(&mctl_com->cr) & 0x1)
 327                 writel(0x00000303, &mctl_ctl->odtmap);
 328         else
 329                 writel(0x00000201, &mctl_ctl->odtmap);
 330
 331         mctl_data_train_cfg(para);
 332         /* ZQ calibration */
 333         clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff);
 334         clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
 335         /* CA calibration */
 336
 337         if (para->dram_type == DRAM_TYPE_DDR3)
 338                 mctl_set_pir(0x0201f3 | 0x1<<10);
 339         else
 340                 mctl_set_pir(0x020173 | 0x1<<10);
 341
 342         /* DQS gate training */
 343         if (mctl_train_dram(para) != 0) {
 344                 low_data_lines_status  = (readl(DXnGSR0(0)) >> 24) & 0x03;
 345                 high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
 346
 347                 if (low_data_lines_status == 0x3)
 348                         return -EIO;
 349
 350                 /* DRAM has only one rank */
 351                 para->rank = 1;
 352                 mctl_set_cr(para);
 353
 354                 if (low_data_lines_status == high_data_lines_status)
 355                         goto done; /* 16 bit bus, 1 rank */
 356
 357                 if (!(low_data_lines_status & high_data_lines_status)) {
 358                         /* Retry 16 bit bus-width with CS1 set */
 359                         para->cs1 = 1;
 360                         mctl_set_cr(para);
 361                         if (mctl_train_dram(para) == 0)
 362                                 goto done;
 363                 }
 364
 365                 /* Try 8 bit bus-width */
 366                 writel(0x0, DXnGCR0(1)); /* Disable high DQ */
 367                 para->cs1 = 0;
 368                 para->bus_width = 8;
 369                 mctl_set_cr(para);
 370                 if (mctl_train_dram(para) != 0)
 371                         return -EIO;
 372         }
 373 done:
 374         /* Check the dramc status */
 375         mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
 376
 377         /* Close DQS gating */
 378         setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
 379
 380         /* set PGCR3,CKE polarity */
 381         writel(0x00aa0060, &mctl_ctl->pgcr3);
 382         /* Enable master access */
 383         writel(0xffffffff, &mctl_com->maer);
 384
 385         return 0;
 386 }
 387
 388 static void mctl_sys_init(struct dram_para *para)
 389 {
 390         struct sunxi_ccm_reg * const ccm =
 391                         (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 392         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 393                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 394
 395         clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
 396         clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
 397         clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 398         clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
 399         clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
 400         udelay(1000);
 401         clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
 402
 403         clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL);
 404
 405         clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
 406                         CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
 407                         CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
 408         mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
 409
 410         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
 411         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 412         setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
 413         setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
 414
 415         para->rank = 2;
 416         para->bus_width = 16;
 417         mctl_set_cr(para);
 418
 419         /* Set dram master access priority */
 420         writel(0x0000e00f, &mctl_ctl->clken);   /* normal */
 421
 422         udelay(250);
 423 }
 424
 425 unsigned long sunxi_dram_init(void)
 426 {
 427         struct sunxi_mctl_com_reg * const mctl_com =
 428                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 429         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 430                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 431
 432         struct dram_para para = {
 433                 .cs1 = 0,
 434                 .bank = 1,
 435                 .rank = 1,
 436                 .rows = 15,
 437                 .bus_width = 16,
 438                 .page_size = 2048,
 439         };
 440
 441 #if defined(CONFIG_MACH_SUN8I_A83T)
 442 #if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7)
 443         para.dram_type = CONFIG_DRAM_TYPE;
 444 #else
 445 #error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3)
 446 #endif
 447 #endif
 448         setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
 449
 450         writel(0, (SUNXI_PRCM_BASE + 0x1e8));
 451         udelay(10);
 452
 453         mctl_sys_init(&para);
 454
 455         if (mctl_channel_init(&para) != 0)
 456                 return 0;
 457
 458         auto_detect_dram_size(&para);
 459
 460         /* Enable master software clk */
 461         writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
 462
 463         /* Set DRAM ODT MAP */
 464         if (para.rank == 2)
 465                 writel(0x00000303, &mctl_ctl->odtmap);
 466         else
 467                 writel(0x00000201, &mctl_ctl->odtmap);
 468
 469         return para.page_size * (para.bus_width / 8) *
 470                 (1 << (para.bank + para.rank + para.rows));
 471 }