arch/arm/mach-sunxi/dram_sun8i_a23.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Sun8i platform dram controller init.
   4  *
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  */
   7
   8 /*
   9  * Note this code uses a lot of magic hex values, that is because this code
  10  * simply replays the init sequence as done by the Allwinner boot0 code, so
  11  * we do not know what these values mean. There are no symbolic constants for
  12  * these magic values, since we do not know how to name them and making up
  13  * names for them is not useful.
  14  *
  15  * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
  16  * found in the TI Keystone2 documentation:
  17  * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
  18  * "Table4-2 DDR3 PHY Registers"
  19  * This may be used as a (possible) reference for future work / cleanups.
  20  */
  21
  22 #include <common.h>
  23 #include <errno.h>
  24 #include <init.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/dram.h>
  28 #include <asm/arch/prcm.h>
  29 #include <linux/delay.h>
  30
  31 static const struct dram_para dram_para = {
  32         .clock = CONFIG_DRAM_CLK,
  33         .type = 3,
  34         .zq = CONFIG_DRAM_ZQ,
  35         .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
  36         .odt_correction = CONFIG_DRAM_ODT_CORRECTION,
  37         .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
  38         .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
  39         .mr0 = 6736,
  40         .mr1 = 4,
  41         .mr2 = 16,
  42         .mr3 = 0,
  43         /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
  44         .tpr0 = 0x2ab83def,
  45         .tpr1 = 0x18082356,
  46         .tpr2 = 0x00034156,
  47         .tpr3 = 0x448c5533,
  48         .tpr4 = 0x08010d00,
  49         .tpr5 = 0x0340b20f,
  50         .tpr6 = 0x20d118cc,
  51         .tpr7 = 0x14062485,
  52         .tpr8 = 0x220d1d52,
  53         .tpr9 = 0x1e078c22,
  54         .tpr10 = 0x3c,
  55         .tpr11 = 0, /* not used */
  56         .tpr12 = 0, /* not used */
  57         .tpr13 = 0x30000,
  58 };
  59
  60 static void mctl_sys_init(void)
  61 {
  62         struct sunxi_ccm_reg * const ccm =
  63                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  64
  65         /* enable pll5, note the divide by 2 is deliberate! */
  66         clock_set_pll5(dram_para.clock * 1000000 / 2,
  67                        dram_para.tpr13 & 0x40000);
  68
  69         /* deassert ahb mctl reset */
  70         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
  71
  72         /* enable ahb mctl clock */
  73         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
  74 }
  75
  76 static void mctl_apply_odt_correction(u32 *reg, int correction)
  77 {
  78         int val;
  79
  80         val = (readl(reg) >> 8) & 0xff;
  81         val += correction;
  82
  83         /* clamp */
  84         if (val < 0)
  85                 val = 0;
  86         else if (val > 255)
  87                 val = 255;
  88
  89         clrsetbits_le32(reg, 0xff00, val << 8);
  90 }
  91
  92 static void mctl_init(u32 *bus_width)
  93 {
  94         struct sunxi_ccm_reg * const ccm =
  95                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  96         struct sunxi_mctl_com_reg * const mctl_com =
  97                 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  98         struct sunxi_mctl_ctl_reg * const mctl_ctl =
  99                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 100         struct sunxi_mctl_phy_reg * const mctl_phy =
 101                 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
 102
 103         if (dram_para.tpr13 & 0x20)
 104                 writel(0x40b, &mctl_phy->dcr);
 105         else
 106                 writel(0x1000040b, &mctl_phy->dcr);
 107
 108         if (dram_para.clock >= 480)
 109                 writel(0x5c000, &mctl_phy->dllgcr);
 110         else
 111                 writel(0xdc000, &mctl_phy->dllgcr);
 112
 113         writel(0x0a003e3f, &mctl_phy->pgcr0);
 114         writel(0x03008421, &mctl_phy->pgcr1);
 115
 116         writel(dram_para.mr0, &mctl_phy->mr0);
 117         writel(dram_para.mr1, &mctl_phy->mr1);
 118         writel(dram_para.mr2, &mctl_phy->mr2);
 119         writel(dram_para.mr3, &mctl_phy->mr3);
 120
 121         if (!(dram_para.tpr13 & 0x10000)) {
 122                 clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000);
 123                 clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000);
 124         }
 125
 126         /*
 127          * All the masking and shifting below converts what I assume are DDR
 128          * timing constants from Allwinner dram_para tpr format to the actual
 129          * timing registers format.
 130          */
 131
 132         writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2);
 133         writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3);
 134         writel((dram_para.tpr0 & 0x3ff00000) >> 2 |
 135                (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4);
 136
 137         writel(dram_para.tpr3, &mctl_phy->dtpr0);
 138         writel(dram_para.tpr4, &mctl_phy->dtpr2);
 139
 140         writel(0x01000081, &mctl_phy->dtcr);
 141
 142         if (dram_para.clock <= 240 || !dram_para.odt_en) {
 143                 clrbits_le32(&mctl_phy->dx0gcr, 0x600);
 144                 clrbits_le32(&mctl_phy->dx1gcr, 0x600);
 145         }
 146         if (dram_para.clock <= 240) {
 147                 writel(0, &mctl_phy->odtcr);
 148                 writel(0, &mctl_ctl->odtmap);
 149         }
 150
 151         writel(((dram_para.tpr5 & 0x0f00) << 12) |
 152                ((dram_para.tpr5 & 0x00f8) <<  9) |
 153                ((dram_para.tpr5 & 0x0007) <<  8),
 154                &mctl_ctl->rfshctl0);
 155
 156         writel(((dram_para.tpr5 & 0x0003f000) << 12) |
 157                ((dram_para.tpr5 & 0x00fc0000) >>  2) |
 158                ((dram_para.tpr5 & 0x3f000000) >> 16) |
 159                ((dram_para.tpr6 & 0x0000003f) >>  0),
 160                &mctl_ctl->dramtmg0);
 161
 162         writel(((dram_para.tpr6 & 0x000007c0) << 10) |
 163                ((dram_para.tpr6 & 0x0000f800) >> 3) |
 164                ((dram_para.tpr6 & 0x003f0000) >> 16),
 165                &mctl_ctl->dramtmg1);
 166
 167         writel(((dram_para.tpr6 & 0x0fc00000) << 2) |
 168                ((dram_para.tpr7 & 0x0000001f) << 16) |
 169                ((dram_para.tpr7 & 0x000003e0) << 3) |
 170                ((dram_para.tpr7 & 0x0000fc00) >> 10),
 171                &mctl_ctl->dramtmg2);
 172
 173         writel(((dram_para.tpr7 & 0x03ff0000) >> 16) |
 174                ((dram_para.tpr6 & 0xf0000000) >> 16),
 175                &mctl_ctl->dramtmg3);
 176
 177         writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) |
 178                ((dram_para.tpr8 & 0x00000007) << 16) |
 179                ((dram_para.tpr8 & 0x00000038) << 5) |
 180                ((dram_para.tpr8 & 0x000003c0) >> 6),
 181                &mctl_ctl->dramtmg4);
 182
 183         writel(((dram_para.tpr8 & 0x00003c00) << 14) |
 184                ((dram_para.tpr8 & 0x0003c000) <<  2) |
 185                ((dram_para.tpr8 & 0x00fc0000) >> 10) |
 186                ((dram_para.tpr8 & 0x0f000000) >> 24),
 187                &mctl_ctl->dramtmg5);
 188
 189         writel(0x00000008, &mctl_ctl->dramtmg8);
 190
 191         writel(((dram_para.tpr8 & 0xf0000000) >> 4) |
 192                ((dram_para.tpr9 & 0x00007c00) << 6) |
 193                ((dram_para.tpr9 & 0x000003e0) << 3) |
 194                ((dram_para.tpr9 & 0x0000001f) >> 0),
 195                &mctl_ctl->pitmg0);
 196
 197         setbits_le32(&mctl_ctl->pitmg1, 0x80000);
 198
 199         writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001,
 200                &mctl_ctl->sched);
 201
 202         writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3);
 203         writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4);
 204
 205         writel(0x00000000, &mctl_ctl->pimisc);
 206         writel(0x80000000, &mctl_ctl->upd0);
 207
 208         writel(((dram_para.tpr9  & 0xffc00000) >> 22) |
 209                ((dram_para.tpr10 & 0x00000fff) << 16),
 210                &mctl_ctl->rfshtmg);
 211
 212         if (dram_para.tpr13 & 0x20)
 213                 writel(0x01040001, &mctl_ctl->mstr);
 214         else
 215                 writel(0x01040401, &mctl_ctl->mstr);
 216
 217         if (!(dram_para.tpr13 & 0x20000)) {
 218                 writel(0x00000002, &mctl_ctl->pwrctl);
 219                 writel(0x00008001, &mctl_ctl->pwrtmg);
 220         }
 221
 222         writel(0x00000001, &mctl_ctl->rfshctl3);
 223         writel(0x00000001, &mctl_ctl->pimisc);
 224
 225         /* deassert dram_clk_cfg reset */
 226         setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
 227
 228         setbits_le32(&mctl_com->ccr, 0x80000);
 229
 230         /* zq stuff */
 231         writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1);
 232
 233         writel(0x00000003, &mctl_phy->pir);
 234         udelay(10);
 235         mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09);
 236
 237         writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2);
 238         writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
 239
 240         /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */
 241         writel(0x000005f3, &mctl_phy->pir);
 242         udelay(10);
 243         mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03);
 244
 245         if (readl(&mctl_phy->dx1gsr0) & 0x1000000) {
 246                 *bus_width = 8;
 247                 writel(0, &mctl_phy->dx1gcr);
 248                 writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
 249                 writel(0x5f3, &mctl_phy->pir);
 250                 udelay(10000);
 251                 setbits_le32(&mctl_ctl->mstr, 0x1000);
 252         } else
 253                 *bus_width = 16;
 254
 255         if (dram_para.odt_correction) {
 256                 mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1,
 257                                           dram_para.odt_correction);
 258                 mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1,
 259                                           dram_para.odt_correction);
 260         }
 261
 262         mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01);
 263
 264         writel(0x08003e3f, &mctl_phy->pgcr0);
 265         writel(0x00000000, &mctl_ctl->rfshctl3);
 266 }
 267
 268 unsigned long sunxi_dram_init(void)
 269 {
 270         struct sunxi_mctl_com_reg * const mctl_com =
 271                 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 272         const u32 columns = 13;
 273         u32 bus, bus_width, offset, page_size, rows;
 274
 275         mctl_sys_init();
 276         mctl_init(&bus_width);
 277
 278         if (bus_width == 16) {
 279                 page_size = 8;
 280                 bus = 1;
 281         } else {
 282                 page_size = 7;
 283                 bus = 0;
 284         }
 285
 286         if (!(dram_para.tpr13 & 0x80000000)) {
 287                 /* Detect and set rows */
 288                 writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size),
 289                        &mctl_com->cr);
 290                 setbits_le32(&mctl_com->swonr, 0x0003ffff);
 291                 for (rows = 11; rows < 16; rows++) {
 292                         offset = 1 << (rows + columns + bus);
 293                         if (mctl_mem_matches(offset))
 294                                 break;
 295                 }
 296                 clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
 297                                 MCTL_CR_ROW(rows));
 298         } else {
 299                 rows = (dram_para.para1 >> 16) & 0xff;
 300                 writel(((dram_para.para2 & 0x000000f0) << 11) |
 301                        ((rows - 1) << 4) |
 302                        ((dram_para.para1 & 0x0f000000) >> 22) |
 303                        0x31000 | MCTL_CR_PAGE_SIZE(page_size),
 304                        &mctl_com->cr);
 305                 setbits_le32(&mctl_com->swonr, 0x0003ffff);
 306         }
 307
 308         /* Setup DRAM master priority? If this is left out things still work */
 309         writel(0x00000008, &mctl_com->mcr0_0);
 310         writel(0x0001000d, &mctl_com->mcr1_0);
 311         writel(0x00000004, &mctl_com->mcr0_1);
 312         writel(0x00000080, &mctl_com->mcr1_1);
 313         writel(0x00000004, &mctl_com->mcr0_2);
 314         writel(0x00000019, &mctl_com->mcr1_2);
 315         writel(0x00000004, &mctl_com->mcr0_3);
 316         writel(0x00000080, &mctl_com->mcr1_3);
 317         writel(0x00000004, &mctl_com->mcr0_4);
 318         writel(0x01010040, &mctl_com->mcr1_4);
 319         writel(0x00000004, &mctl_com->mcr0_5);
 320         writel(0x0001002f, &mctl_com->mcr1_5);
 321         writel(0x00000004, &mctl_com->mcr0_6);
 322         writel(0x00010020, &mctl_com->mcr1_6);
 323         writel(0x00000004, &mctl_com->mcr0_7);
 324         writel(0x00010020, &mctl_com->mcr1_7);
 325         writel(0x00000008, &mctl_com->mcr0_8);
 326         writel(0x00000001, &mctl_com->mcr1_8);
 327         writel(0x00000008, &mctl_com->mcr0_9);
 328         writel(0x00000005, &mctl_com->mcr1_9);
 329         writel(0x00000008, &mctl_com->mcr0_10);
 330         writel(0x00000003, &mctl_com->mcr1_10);
 331         writel(0x00000008, &mctl_com->mcr0_11);
 332         writel(0x00000005, &mctl_com->mcr1_11);
 333         writel(0x00000008, &mctl_com->mcr0_12);
 334         writel(0x00000003, &mctl_com->mcr1_12);
 335         writel(0x00000008, &mctl_com->mcr0_13);
 336         writel(0x00000004, &mctl_com->mcr1_13);
 337         writel(0x00000008, &mctl_com->mcr0_14);
 338         writel(0x00000002, &mctl_com->mcr1_14);
 339         writel(0x00000008, &mctl_com->mcr0_15);
 340         writel(0x00000003, &mctl_com->mcr1_15);
 341         writel(0x00010138, &mctl_com->bwcr);
 342
 343         return 1 << (rows + columns + bus);
 344 }