arch/arm/mach-sunxi/dram_sun50i_h6.c

   1 /*
   2  * sun50i H6 platform dram controller init
   3  *
   4  * (C) Copyright 2017      Icenowy Zheng <icenowy@aosc.io>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/dram.h>
  12 #include <asm/arch/cpu.h>
  13 #include <linux/bitops.h>
  14 #include <linux/kconfig.h>
  15
  16 /*
  17  * The DRAM controller structure on H6 is similar to the ones on A23/A80:
  18  * they all contains 3 parts, COM, CTL and PHY. (As a note on A33/A83T/H3/A64
  19  * /H5/R40 CTL and PHY is composed).
  20  *
  21  * COM is allwinner-specific. On H6, the address mapping function is moved
  22  * from COM to CTL (with the standard ADDRMAP registers on DesignWare memory
  23  * controller).
  24  *
  25  * CTL (controller) and PHY is from DesignWare.
  26  *
  27  * The CTL part is a bit similar to the one on A23/A80 (because they all
  28  * originate from DesignWare), but gets more registers added.
  29  *
  30  * The PHY part is quite new, not seen in any previous Allwinner SoCs, and
  31  * not seen on other SoCs in U-Boot. The only SoC that is also known to have
  32  * similar PHY is ZynqMP.
  33  */
  34
  35 static void mctl_sys_init(struct dram_para *para);
  36 static void mctl_com_init(struct dram_para *para);
  37 static void mctl_channel_init(struct dram_para *para);
  38
  39 static void mctl_core_init(struct dram_para *para)
  40 {
  41         mctl_sys_init(para);
  42         mctl_com_init(para);
  43         switch (para->type) {
  44         case SUNXI_DRAM_TYPE_LPDDR3:
  45         case SUNXI_DRAM_TYPE_DDR3:
  46                 mctl_set_timing_params(para);
  47                 break;
  48         default:
  49                 panic("Unsupported DRAM type!");
  50         };
  51         mctl_channel_init(para);
  52 }
  53
  54 /* PHY initialisation */
  55 static void mctl_phy_pir_init(u32 val)
  56 {
  57         struct sunxi_mctl_phy_reg * const mctl_phy =
  58                         (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
  59
  60         writel(val, &mctl_phy->pir);
  61         writel(val | BIT(0), &mctl_phy->pir);   /* Start initialisation. */
  62         mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
  63 }
  64
  65 enum {
  66         MBUS_PORT_CPU           = 0,
  67         MBUS_PORT_GPU           = 1,
  68         MBUS_PORT_MAHB          = 2,
  69         MBUS_PORT_DMA           = 3,
  70         MBUS_PORT_VE            = 4,
  71         MBUS_PORT_CE            = 5,
  72         MBUS_PORT_TSC0          = 6,
  73         MBUS_PORT_NDFC0         = 8,
  74         MBUS_PORT_CSI0          = 11,
  75         MBUS_PORT_DI0           = 14,
  76         MBUS_PORT_DI1           = 15,
  77         MBUS_PORT_DE300         = 16,
  78         MBUS_PORT_IOMMU         = 25,
  79         MBUS_PORT_VE2           = 26,
  80         MBUS_PORT_USB3        = 37,
  81         MBUS_PORT_PCIE          = 38,
  82         MBUS_PORT_VP9           = 39,
  83         MBUS_PORT_HDCP2       = 40,
  84 };
  85
  86 enum {
  87         MBUS_QOS_LOWEST = 0,
  88         MBUS_QOS_LOW,
  89         MBUS_QOS_HIGH,
  90         MBUS_QOS_HIGHEST
  91 };
  92 inline void mbus_configure_port(u8 port,
  93                                 bool bwlimit,
  94                                 bool priority,
  95                                 u8 qos,
  96                                 u8 waittime,
  97                                 u8 acs,
  98                                 u16 bwl0,
  99                                 u16 bwl1,
 100                                 u16 bwl2)
 101 {
 102         struct sunxi_mctl_com_reg * const mctl_com =
 103                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 104
 105         const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
 106                            | (priority ? (1 << 1) : 0)
 107                            | ((qos & 0x3) << 2)
 108                            | ((waittime & 0xf) << 4)
 109                            | ((acs & 0xff) << 8)
 110                            | (bwl0 << 16) );
 111         const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
 112
 113         debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
 114         writel(cfg0, &mctl_com->master[port].cfg0);
 115         writel(cfg1, &mctl_com->master[port].cfg1);
 116 }
 117
 118 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2)    \
 119         mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
 120                             MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
 121
 122 static void mctl_set_master_priority(void)
 123 {
 124         struct sunxi_mctl_com_reg * const mctl_com =
 125                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 126
 127         /* enable bandwidth limit windows and set windows size 1us */
 128         writel(399, &mctl_com->tmr);
 129         writel(BIT(16), &mctl_com->bwcr);
 130
 131         MBUS_CONF(  CPU,  true, HIGHEST, 0,  256,  128,  100);
 132         MBUS_CONF(  GPU,  true,    HIGH, 0, 1536, 1400,  256);
 133         MBUS_CONF( MAHB,  true, HIGHEST, 0,  512,  256,   96);
 134         MBUS_CONF(  DMA,  true,    HIGH, 0,  256,  100,   80);
 135         MBUS_CONF(   VE,  true,    HIGH, 2, 8192, 5500, 5000);
 136         MBUS_CONF(   CE,  true,    HIGH, 2,  100,   64,   32);
 137         MBUS_CONF( TSC0,  true,    HIGH, 2,  100,   64,   32);
 138         MBUS_CONF(NDFC0,  true,    HIGH, 0,  256,  128,   64);
 139         MBUS_CONF( CSI0,  true,    HIGH, 0,  256,  128,  100);
 140         MBUS_CONF(  DI0,  true,    HIGH, 0, 1024,  256,   64);
 141         MBUS_CONF(DE300,  true, HIGHEST, 6, 8192, 2800, 2400);
 142         MBUS_CONF(IOMMU,  true, HIGHEST, 0,  100,   64,   32);
 143         MBUS_CONF(  VE2,  true,    HIGH, 2, 8192, 5500, 5000);
 144         MBUS_CONF( USB3,  true,    HIGH, 0,  256,  128,   64);
 145         MBUS_CONF( PCIE,  true,    HIGH, 2,  100,   64,   32);
 146         MBUS_CONF(  VP9,  true,    HIGH, 2, 8192, 5500, 5000);
 147         MBUS_CONF(HDCP2,  true,    HIGH, 2,  100,   64,   32);
 148 }
 149
 150 static void mctl_sys_init(struct dram_para *para)
 151 {
 152         struct sunxi_ccm_reg * const ccm =
 153                         (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 154         struct sunxi_mctl_com_reg * const mctl_com =
 155                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 156         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 157                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 158
 159         /* Put all DRAM-related blocks to reset state */
 160         clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
 161         clrbits_le32(&ccm->dram_gate_reset, BIT(0));
 162         udelay(5);
 163         writel(0, &ccm->dram_gate_reset);
 164         clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
 165         clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
 166
 167         udelay(5);
 168
 169         /* Set PLL5 rate to doubled DRAM clock rate */
 170         writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
 171                CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
 172         mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
 173
 174         /* Configure DRAM mod clock */
 175         writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
 176         setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
 177         writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
 178         udelay(5);
 179         setbits_le32(&ccm->dram_gate_reset, BIT(0));
 180
 181         /* Disable all channels */
 182         writel(0, &mctl_com->maer0);
 183         writel(0, &mctl_com->maer1);
 184         writel(0, &mctl_com->maer2);
 185
 186         /* Configure MBUS and enable DRAM mod reset */
 187         setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
 188         setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
 189         setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
 190         udelay(5);
 191
 192         /* Unknown hack from the BSP, which enables access of mctl_ctl regs */
 193         writel(0x8000, &mctl_ctl->unk_0x00c);
 194 }
 195
 196 static void mctl_set_addrmap(struct dram_para *para)
 197 {
 198         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 199                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 200         u8 cols = para->cols;
 201         u8 rows = para->rows;
 202         u8 ranks = para->ranks;
 203
 204         if (!para->bus_full_width)
 205                 cols -= 1;
 206
 207         /* Ranks */
 208         if (ranks == 2)
 209                 mctl_ctl->addrmap[0] = rows + cols - 3;
 210         else
 211                 mctl_ctl->addrmap[0] = 0x1F;
 212
 213         /* Banks, hardcoded to 8 banks now */
 214         mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;
 215
 216         /* Columns */
 217         mctl_ctl->addrmap[2] = 0;
 218         switch (cols) {
 219         case 7:
 220                 mctl_ctl->addrmap[3] = 0x1F1F1F00;
 221                 mctl_ctl->addrmap[4] = 0x1F1F;
 222                 break;
 223         case 8:
 224                 mctl_ctl->addrmap[3] = 0x1F1F0000;
 225                 mctl_ctl->addrmap[4] = 0x1F1F;
 226                 break;
 227         case 9:
 228                 mctl_ctl->addrmap[3] = 0x1F000000;
 229                 mctl_ctl->addrmap[4] = 0x1F1F;
 230                 break;
 231         case 10:
 232                 mctl_ctl->addrmap[3] = 0;
 233                 mctl_ctl->addrmap[4] = 0x1F1F;
 234                 break;
 235         case 11:
 236                 mctl_ctl->addrmap[3] = 0;
 237                 mctl_ctl->addrmap[4] = 0x1F00;
 238                 break;
 239         case 12:
 240                 mctl_ctl->addrmap[3] = 0;
 241                 mctl_ctl->addrmap[4] = 0;
 242                 break;
 243         default:
 244                 panic("Unsupported DRAM configuration: column number invalid\n");
 245         }
 246
 247         /* Rows */
 248         mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
 249         switch (rows) {
 250         case 13:
 251                 mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;
 252                 mctl_ctl->addrmap[7] = 0x0F0F;
 253                 break;
 254         case 14:
 255                 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;
 256                 mctl_ctl->addrmap[7] = 0x0F0F;
 257                 break;
 258         case 15:
 259                 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;
 260                 mctl_ctl->addrmap[7] = 0x0F0F;
 261                 break;
 262         case 16:
 263                 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
 264                 mctl_ctl->addrmap[7] = 0x0F0F;
 265                 break;
 266         case 17:
 267                 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
 268                 mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;
 269                 break;
 270         case 18:
 271                 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
 272                 mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);
 273                 break;
 274         default:
 275                 panic("Unsupported DRAM configuration: row number invalid\n");
 276         }
 277
 278         /* Bank groups, DDR4 only */
 279         mctl_ctl->addrmap[8] = 0x3F3F;
 280 }
 281
 282 static void mctl_com_init(struct dram_para *para)
 283 {
 284         struct sunxi_mctl_com_reg * const mctl_com =
 285                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 286         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 287                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 288         struct sunxi_mctl_phy_reg * const mctl_phy =
 289                         (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
 290         u32 reg_val, tmp;
 291
 292         mctl_set_addrmap(para);
 293
 294         setbits_le32(&mctl_com->cr, BIT(31));
 295
 296         /* The bonding ID seems to be always 7. */
 297         if (readl(SUNXI_SIDC_BASE + 0x100) == 7)        /* bonding ID */
 298                 clrbits_le32(&mctl_com->cr, BIT(27));
 299         else if (readl(SUNXI_SIDC_BASE + 0x100) == 3)
 300                 setbits_le32(&mctl_com->cr, BIT(27));
 301
 302         if (para->clk > 408)
 303                 reg_val = 0xf00;
 304         else if (para->clk > 246)
 305                 reg_val = 0x1f00;
 306         else
 307                 reg_val = 0x3f00;
 308         clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
 309
 310         /* TODO: DDR4 */
 311         reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
 312         if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
 313                 reg_val |= MSTR_DEVICETYPE_LPDDR3;
 314         if (para->type == SUNXI_DRAM_TYPE_DDR3)
 315                 reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
 316         if (para->bus_full_width)
 317                 reg_val |= MSTR_BUSWIDTH_FULL;
 318         else
 319                 reg_val |= MSTR_BUSWIDTH_HALF;
 320         writel(reg_val | BIT(31), &mctl_ctl->mstr);
 321
 322         if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
 323                 reg_val = DCR_LPDDR3 | DCR_DDR8BANK;
 324         if (para->type == SUNXI_DRAM_TYPE_DDR3)
 325                 reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
 326         writel(reg_val | 0x400, &mctl_phy->dcr);
 327
 328         if (para->ranks == 2)
 329                 writel(0x0303, &mctl_ctl->odtmap);
 330         else
 331                 writel(0x0201, &mctl_ctl->odtmap);
 332
 333         /* TODO: DDR4 */
 334         if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
 335                 tmp = para->clk * 7 / 2000;
 336                 reg_val = 0x0400;
 337                 reg_val |= (tmp + 7) << 24;
 338                 reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
 339         } else if (para->type == SUNXI_DRAM_TYPE_DDR3) {
 340                 reg_val = 0x06000400;   /* TODO?: Use CL - CWL value in [7:0] */
 341         } else {
 342                 panic("Only (LP)DDR3 supported (type = %d)\n", para->type);
 343         }
 344         writel(reg_val, &mctl_ctl->odtcfg);
 345
 346         if (!para->bus_full_width) {
 347                 writel(0x0, &mctl_phy->dx[2].gcr[0]);
 348                 writel(0x0, &mctl_phy->dx[3].gcr[0]);
 349         }
 350 }
 351
 352 static void mctl_bit_delay_set(struct dram_para *para)
 353 {
 354         struct sunxi_mctl_phy_reg * const mctl_phy =
 355                         (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
 356         int i, j;
 357         u32 val;
 358
 359         for (i = 0; i < 4; i++) {
 360                 val = readl(&mctl_phy->dx[i].bdlr0);
 361                 for (j = 0; j < 4; j++)
 362                         val += para->dx_write_delays[i][j] << (j * 8);
 363                 writel(val, &mctl_phy->dx[i].bdlr0);
 364
 365                 val = readl(&mctl_phy->dx[i].bdlr1);
 366                 for (j = 0; j < 4; j++)
 367                         val += para->dx_write_delays[i][j + 4] << (j * 8);
 368                 writel(val, &mctl_phy->dx[i].bdlr1);
 369
 370                 val = readl(&mctl_phy->dx[i].bdlr2);
 371                 for (j = 0; j < 4; j++)
 372                         val += para->dx_write_delays[i][j + 8] << (j * 8);
 373                 writel(val, &mctl_phy->dx[i].bdlr2);
 374         }
 375         clrbits_le32(&mctl_phy->pgcr[0], BIT(26));
 376
 377         for (i = 0; i < 4; i++) {
 378                 val = readl(&mctl_phy->dx[i].bdlr3);
 379                 for (j = 0; j < 4; j++)
 380                         val += para->dx_read_delays[i][j] << (j * 8);
 381                 writel(val, &mctl_phy->dx[i].bdlr3);
 382
 383                 val = readl(&mctl_phy->dx[i].bdlr4);
 384                 for (j = 0; j < 4; j++)
 385                         val += para->dx_read_delays[i][j + 4] << (j * 8);
 386                 writel(val, &mctl_phy->dx[i].bdlr4);
 387
 388                 val = readl(&mctl_phy->dx[i].bdlr5);
 389                 for (j = 0; j < 4; j++)
 390                         val += para->dx_read_delays[i][j + 8] << (j * 8);
 391                 writel(val, &mctl_phy->dx[i].bdlr5);
 392
 393                 val = readl(&mctl_phy->dx[i].bdlr6);
 394                 val += (para->dx_read_delays[i][12] << 8) |
 395                        (para->dx_read_delays[i][13] << 16);
 396                 writel(val, &mctl_phy->dx[i].bdlr6);
 397         }
 398         setbits_le32(&mctl_phy->pgcr[0], BIT(26));
 399         udelay(1);
 400
 401         if (para->type != SUNXI_DRAM_TYPE_LPDDR3)
 402                 return;
 403
 404         for (i = 1; i < 14; i++) {
 405                 val = readl(&mctl_phy->acbdlr[i]);
 406                 val += 0x0a0a0a0a;
 407                 writel(val, &mctl_phy->acbdlr[i]);
 408         }
 409 }
 410
 411 static void mctl_channel_init(struct dram_para *para)
 412 {
 413         struct sunxi_mctl_com_reg * const mctl_com =
 414                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 415         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 416                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 417         struct sunxi_mctl_phy_reg * const mctl_phy =
 418                         (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
 419         int i;
 420         u32 val;
 421
 422         setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));
 423         setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));
 424         writel(0x2f05, &mctl_ctl->sched[0]);
 425         setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
 426         setbits_le32(&mctl_ctl->dfimisc, BIT(0));
 427         setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));
 428         clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0);
 429         /* TODO: non-LPDDR3 types */
 430         clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800));
 431         clrbits_le32(&mctl_phy->pgcr[6], BIT(0));
 432         clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220);
 433         /* TODO: VT compensation */
 434         clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060);
 435         clrbits_le32(&mctl_phy->vtcr[1], BIT(1));
 436
 437         for (i = 0; i < 4; i++)
 438                 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800);
 439         for (i = 0; i < 4; i++)
 440                 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555);
 441         for (i = 0; i < 4; i++)
 442                 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010);
 443
 444         udelay(100);
 445
 446         if (para->ranks == 2)
 447                 setbits_le32(&mctl_phy->dtcr[1], 0x30000);
 448         else
 449                 clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
 450
 451         if (sunxi_dram_is_lpddr(para->type))
 452                 clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
 453         if (para->ranks == 2) {
 454                 writel(0x00010001, &mctl_phy->rankidr);
 455                 writel(0x20000, &mctl_phy->odtcr);
 456         } else {
 457                 writel(0x0, &mctl_phy->rankidr);
 458                 writel(0x10000, &mctl_phy->odtcr);
 459         }
 460
 461         /* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */
 462         if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
 463                 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
 464         else
 465                 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000);
 466         if (para->clk <= 792) {
 467                 if (para->clk <= 672) {
 468                         if (para->clk <= 600)
 469                                 val = 0x300;
 470                         else
 471                                 val = 0x400;
 472                 } else {
 473                         val = 0x500;
 474                 }
 475         } else {
 476                 val = 0x600;
 477         }
 478         /* FIXME: NOT REVIEWED YET */
 479         clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val);
 480         clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff,
 481                         CONFIG_DRAM_ZQ & 0xff);
 482         clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);
 483         setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);
 484         setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);
 485         setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);
 486         clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);
 487         setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);
 488         setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);
 489         setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);
 490         if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
 491                 for (i = 1; i < 14; i++)
 492                         writel(0x06060606, &mctl_phy->acbdlr[i]);
 493         }
 494
 495         val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE |
 496               PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE;
 497         if (para->type == SUNXI_DRAM_TYPE_DDR3)
 498                 val |= PIR_DRAMRST | PIR_WL;
 499         mctl_phy_pir_init(val);
 500
 501         /* TODO: DDR4 types ? */
 502         for (i = 0; i < 4; i++)
 503                 writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
 504
 505         for (i = 0; i < 4; i++) {
 506                 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
 507                         val = 0x0;
 508                 else
 509                         val = 0xaaaa;
 510                 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val);
 511
 512                 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
 513                         val = 0x0;
 514                 else
 515                         val = 0x2020;
 516                 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val);
 517         }
 518
 519         mctl_bit_delay_set(para);
 520         udelay(1);
 521
 522         setbits_le32(&mctl_phy->pgcr[6], BIT(0));
 523         clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);
 524         for (i = 0; i < 4; i++)
 525                 clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
 526         udelay(10);
 527
 528         if (readl(&mctl_phy->pgsr[0]) & 0x400000)
 529         {
 530                 /* Check for single rank and optionally half DQ. */
 531                 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
 532                     (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
 533                         para->ranks = 1;
 534
 535                         if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
 536                             (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
 537                                 para->bus_full_width = 0;
 538
 539                         /* Restart DRAM initialization from scratch. */
 540                         mctl_core_init(para);
 541                         return;
 542                 }
 543
 544                 /*
 545                  * Check for dual rank and half DQ. NOTE: This combination
 546                  * is highly unlikely and was not tested. Condition is the
 547                  * same as in libdram, though.
 548                  */
 549                 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
 550                     (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
 551                         para->bus_full_width = 0;
 552
 553                         /* Restart DRAM initialization from scratch. */
 554                         mctl_core_init(para);
 555                         return;
 556                 }
 557
 558                 panic("This DRAM setup is currently not supported.\n");
 559         }
 560
 561         if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
 562                 /* Oops! There's something wrong! */
 563                 debug("PLL = %x\n", readl(0x3001010));
 564                 debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
 565                 for (i = 0; i < 4; i++)
 566                         debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
 567                 panic("Error while initializing DRAM PHY!\n");
 568         }
 569
 570         if (sunxi_dram_is_lpddr(para->type))
 571                 clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
 572         clrbits_le32(&mctl_phy->pgcr[1], 0x40);
 573         clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
 574         writel(1, &mctl_ctl->swctl);
 575         mctl_await_completion(&mctl_ctl->swstat, 1, 1);
 576         clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));
 577
 578         setbits_le32(&mctl_com->unk_0x014, BIT(31));
 579         writel(0xffffffff, &mctl_com->maer0);
 580         writel(0x7ff, &mctl_com->maer1);
 581         writel(0xffff, &mctl_com->maer2);
 582 }
 583
 584 static void mctl_auto_detect_dram_size(struct dram_para *para)
 585 {
 586         /* TODO: non-(LP)DDR3 */
 587         /* Detect rank number and half DQ by the code in mctl_channel_init. */
 588         mctl_core_init(para);
 589
 590         /* detect row address bits */
 591         para->cols = 8;
 592         para->rows = 18;
 593         mctl_core_init(para);
 594
 595         for (para->rows = 13; para->rows < 18; para->rows++) {
 596                 /* 8 banks, 8 bit per byte and 16/32 bit width */
 597                 if (mctl_mem_matches((1 << (para->rows + para->cols +
 598                                             4 + para->bus_full_width))))
 599                         break;
 600         }
 601
 602         /* detect column address bits */
 603         para->cols = 11;
 604         mctl_core_init(para);
 605
 606         for (para->cols = 8; para->cols < 11; para->cols++) {
 607                 /* 8 bits per byte and 16/32 bit width */
 608                 if (mctl_mem_matches(1 << (para->cols + 1 +
 609                                            para->bus_full_width)))
 610                         break;
 611         }
 612 }
 613
 614 unsigned long mctl_calc_size(struct dram_para *para)
 615 {
 616         u8 width = para->bus_full_width ? 4 : 2;
 617
 618         /* TODO: non-(LP)DDR3 */
 619
 620         /* 8 banks */
 621         return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
 622 }
 623
 624 #define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS                        \
 625         {{  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 626          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 627          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  4,  4,  0 },    \
 628          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 }}
 629 #define SUN50I_H6_LPDDR3_DX_READ_DELAYS                                 \
 630         {{  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
 631          {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
 632          {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
 633          {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 }}
 634
 635 #define SUN50I_H6_DDR3_DX_WRITE_DELAYS                          \
 636         {{  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 637          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 638          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 639          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 }}
 640 #define SUN50I_H6_DDR3_DX_READ_DELAYS                                   \
 641         {{  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 642          {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
 643          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 644          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 }}
 645
 646 unsigned long sunxi_dram_init(void)
 647 {
 648         struct sunxi_mctl_com_reg * const mctl_com =
 649                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 650         struct dram_para para = {
 651                 .clk = CONFIG_DRAM_CLK,
 652                 .ranks = 2,
 653                 .cols = 11,
 654                 .rows = 14,
 655                 .bus_full_width = 1,
 656 #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
 657                 .type = SUNXI_DRAM_TYPE_LPDDR3,
 658                 .dx_read_delays  = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
 659                 .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
 660 #elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
 661                 .type = SUNXI_DRAM_TYPE_DDR3,
 662                 .dx_read_delays  = SUN50I_H6_DDR3_DX_READ_DELAYS,
 663                 .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
 664 #endif
 665         };
 666
 667         unsigned long size;
 668
 669         /* RES_CAL_CTRL_REG in BSP U-boot*/
 670         setbits_le32(0x7010310, BIT(8));
 671         clrbits_le32(0x7010318, 0x3f);
 672
 673         mctl_auto_detect_dram_size(&para);
 674
 675         mctl_core_init(&para);
 676
 677         size = mctl_calc_size(&para);
 678
 679         clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
 680
 681         mctl_set_master_priority();
 682
 683         return size;
 684 };