arch/arm/mach-sunxi/dram_sun50i_h6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * sun50i H6 platform dram controller init
   4  *
   5  * (C) Copyright 2017      Icenowy Zheng <icenowy@aosc.io>
   6  *
   7  */
   8 #include <common.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/dram.h>
  14 #include <asm/arch/cpu.h>
  15 #include <linux/bitops.h>
  16 #include <linux/kconfig.h>
  17
  18 /*
  19  * The DRAM controller structure on H6 is similar to the ones on A23/A80:
  20  * they all contains 3 parts, COM, CTL and PHY. (As a note on A33/A83T/H3/A64
  21  * /H5/R40 CTL and PHY is composed).
  22  *
  23  * COM is allwinner-specific. On H6, the address mapping function is moved
  24  * from COM to CTL (with the standard ADDRMAP registers on DesignWare memory
  25  * controller).
  26  *
  27  * CTL (controller) and PHY is from DesignWare.
  28  *
  29  * The CTL part is a bit similar to the one on A23/A80 (because they all
  30  * originate from DesignWare), but gets more registers added.
  31  *
  32  * The PHY part is quite new, not seen in any previous Allwinner SoCs, and
  33  * not seen on other SoCs in U-Boot. The only SoC that is also known to have
  34  * similar PHY is ZynqMP.
  35  */
  36
  37 static void mctl_sys_init(struct dram_para *para);
  38 static void mctl_com_init(struct dram_para *para);
  39 static void mctl_channel_init(struct dram_para *para);
  40
  41 static void mctl_core_init(struct dram_para *para)
  42 {
  43         mctl_sys_init(para);
  44         mctl_com_init(para);
  45         switch (para->type) {
  46         case SUNXI_DRAM_TYPE_LPDDR3:
  47         case SUNXI_DRAM_TYPE_DDR3:
  48                 mctl_set_timing_params(para);
  49                 break;
  50         default:
  51                 panic("Unsupported DRAM type!");
  52         };
  53         mctl_channel_init(para);
  54 }
  55
  56 /* PHY initialisation */
  57 static void mctl_phy_pir_init(u32 val)
  58 {
  59         struct sunxi_mctl_phy_reg * const mctl_phy =
  60                         (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
  61
  62         writel(val, &mctl_phy->pir);
  63         writel(val | BIT(0), &mctl_phy->pir);   /* Start initialisation. */
  64         mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
  65 }
  66
  67 enum {
  68         MBUS_PORT_CPU           = 0,
  69         MBUS_PORT_GPU           = 1,
  70         MBUS_PORT_MAHB          = 2,
  71         MBUS_PORT_DMA           = 3,
  72         MBUS_PORT_VE            = 4,
  73         MBUS_PORT_CE            = 5,
  74         MBUS_PORT_TSC0          = 6,
  75         MBUS_PORT_NDFC0         = 8,
  76         MBUS_PORT_CSI0          = 11,
  77         MBUS_PORT_DI0           = 14,
  78         MBUS_PORT_DI1           = 15,
  79         MBUS_PORT_DE300         = 16,
  80         MBUS_PORT_IOMMU         = 25,
  81         MBUS_PORT_VE2           = 26,
  82         MBUS_PORT_USB3        = 37,
  83         MBUS_PORT_PCIE          = 38,
  84         MBUS_PORT_VP9           = 39,
  85         MBUS_PORT_HDCP2       = 40,
  86 };
  87
  88 enum {
  89         MBUS_QOS_LOWEST = 0,
  90         MBUS_QOS_LOW,
  91         MBUS_QOS_HIGH,
  92         MBUS_QOS_HIGHEST
  93 };
  94 inline void mbus_configure_port(u8 port,
  95                                 bool bwlimit,
  96                                 bool priority,
  97                                 u8 qos,
  98                                 u8 waittime,
  99                                 u8 acs,
 100                                 u16 bwl0,
 101                                 u16 bwl1,
 102                                 u16 bwl2)
 103 {
 104         struct sunxi_mctl_com_reg * const mctl_com =
 105                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 106
 107         const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
 108                            | (priority ? (1 << 1) : 0)
 109                            | ((qos & 0x3) << 2)
 110                            | ((waittime & 0xf) << 4)
 111                            | ((acs & 0xff) << 8)
 112                            | (bwl0 << 16) );
 113         const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
 114
 115         debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
 116         writel(cfg0, &mctl_com->master[port].cfg0);
 117         writel(cfg1, &mctl_com->master[port].cfg1);
 118 }
 119
 120 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2)    \
 121         mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
 122                             MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
 123
 124 static void mctl_set_master_priority(void)
 125 {
 126         struct sunxi_mctl_com_reg * const mctl_com =
 127                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 128
 129         /* enable bandwidth limit windows and set windows size 1us */
 130         writel(399, &mctl_com->tmr);
 131         writel(BIT(16), &mctl_com->bwcr);
 132
 133         MBUS_CONF(  CPU,  true, HIGHEST, 0,  256,  128,  100);
 134         MBUS_CONF(  GPU,  true,    HIGH, 0, 1536, 1400,  256);
 135         MBUS_CONF( MAHB,  true, HIGHEST, 0,  512,  256,   96);
 136         MBUS_CONF(  DMA,  true,    HIGH, 0,  256,  100,   80);
 137         MBUS_CONF(   VE,  true,    HIGH, 2, 8192, 5500, 5000);
 138         MBUS_CONF(   CE,  true,    HIGH, 2,  100,   64,   32);
 139         MBUS_CONF( TSC0,  true,    HIGH, 2,  100,   64,   32);
 140         MBUS_CONF(NDFC0,  true,    HIGH, 0,  256,  128,   64);
 141         MBUS_CONF( CSI0,  true,    HIGH, 0,  256,  128,  100);
 142         MBUS_CONF(  DI0,  true,    HIGH, 0, 1024,  256,   64);
 143         MBUS_CONF(DE300,  true, HIGHEST, 6, 8192, 2800, 2400);
 144         MBUS_CONF(IOMMU,  true, HIGHEST, 0,  100,   64,   32);
 145         MBUS_CONF(  VE2,  true,    HIGH, 2, 8192, 5500, 5000);
 146         MBUS_CONF( USB3,  true,    HIGH, 0,  256,  128,   64);
 147         MBUS_CONF( PCIE,  true,    HIGH, 2,  100,   64,   32);
 148         MBUS_CONF(  VP9,  true,    HIGH, 2, 8192, 5500, 5000);
 149         MBUS_CONF(HDCP2,  true,    HIGH, 2,  100,   64,   32);
 150 }
 151
 152 static void mctl_sys_init(struct dram_para *para)
 153 {
 154         struct sunxi_ccm_reg * const ccm =
 155                         (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 156         struct sunxi_mctl_com_reg * const mctl_com =
 157                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 158         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 159                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 160
 161         /* Put all DRAM-related blocks to reset state */
 162         clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
 163         clrbits_le32(&ccm->dram_gate_reset, BIT(0));
 164         udelay(5);
 165         writel(0, &ccm->dram_gate_reset);
 166         clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
 167         clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
 168
 169         udelay(5);
 170
 171         /* Set PLL5 rate to doubled DRAM clock rate */
 172         writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
 173                CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
 174         mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
 175
 176         /* Configure DRAM mod clock */
 177         writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
 178         setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
 179         writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
 180         udelay(5);
 181         setbits_le32(&ccm->dram_gate_reset, BIT(0));
 182
 183         /* Disable all channels */
 184         writel(0, &mctl_com->maer0);
 185         writel(0, &mctl_com->maer1);
 186         writel(0, &mctl_com->maer2);
 187
 188         /* Configure MBUS and enable DRAM mod reset */
 189         setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
 190         setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
 191         setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
 192         udelay(5);
 193
 194         /* Unknown hack from the BSP, which enables access of mctl_ctl regs */
 195         writel(0x8000, &mctl_ctl->unk_0x00c);
 196 }
 197
 198 static void mctl_set_addrmap(struct dram_para *para)
 199 {
 200         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 201                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 202         u8 cols = para->cols;
 203         u8 rows = para->rows;
 204         u8 ranks = para->ranks;
 205
 206         if (!para->bus_full_width)
 207                 cols -= 1;
 208
 209         /* Ranks */
 210         if (ranks == 2)
 211                 mctl_ctl->addrmap[0] = rows + cols - 3;
 212         else
 213                 mctl_ctl->addrmap[0] = 0x1F;
 214
 215         /* Banks, hardcoded to 8 banks now */
 216         mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;
 217
 218         /* Columns */
 219         mctl_ctl->addrmap[2] = 0;
 220         switch (cols) {
 221         case 7:
 222                 mctl_ctl->addrmap[3] = 0x1F1F1F00;
 223                 mctl_ctl->addrmap[4] = 0x1F1F;
 224                 break;
 225         case 8:
 226                 mctl_ctl->addrmap[3] = 0x1F1F0000;
 227                 mctl_ctl->addrmap[4] = 0x1F1F;
 228                 break;
 229         case 9:
 230                 mctl_ctl->addrmap[3] = 0x1F000000;
 231                 mctl_ctl->addrmap[4] = 0x1F1F;
 232                 break;
 233         case 10:
 234                 mctl_ctl->addrmap[3] = 0;
 235                 mctl_ctl->addrmap[4] = 0x1F1F;
 236                 break;
 237         case 11:
 238                 mctl_ctl->addrmap[3] = 0;
 239                 mctl_ctl->addrmap[4] = 0x1F00;
 240                 break;
 241         case 12:
 242                 mctl_ctl->addrmap[3] = 0;
 243                 mctl_ctl->addrmap[4] = 0;
 244                 break;
 245         default:
 246                 panic("Unsupported DRAM configuration: column number invalid\n");
 247         }
 248
 249         /* Rows */
 250         mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
 251         switch (rows) {
 252         case 13:
 253                 mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;
 254                 mctl_ctl->addrmap[7] = 0x0F0F;
 255                 break;
 256         case 14:
 257                 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;
 258                 mctl_ctl->addrmap[7] = 0x0F0F;
 259                 break;
 260         case 15:
 261                 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;
 262                 mctl_ctl->addrmap[7] = 0x0F0F;
 263                 break;
 264         case 16:
 265                 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
 266                 mctl_ctl->addrmap[7] = 0x0F0F;
 267                 break;
 268         case 17:
 269                 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
 270                 mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;
 271                 break;
 272         case 18:
 273                 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
 274                 mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);
 275                 break;
 276         default:
 277                 panic("Unsupported DRAM configuration: row number invalid\n");
 278         }
 279
 280         /* Bank groups, DDR4 only */
 281         mctl_ctl->addrmap[8] = 0x3F3F;
 282 }
 283
 284 static void mctl_com_init(struct dram_para *para)
 285 {
 286         struct sunxi_mctl_com_reg * const mctl_com =
 287                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 288         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 289                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 290         struct sunxi_mctl_phy_reg * const mctl_phy =
 291                         (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
 292         u32 reg_val, tmp;
 293
 294         mctl_set_addrmap(para);
 295
 296         setbits_le32(&mctl_com->cr, BIT(31));
 297
 298         /* The bonding ID seems to be always 7. */
 299         if (readl(SUNXI_SIDC_BASE + 0x100) == 7)        /* bonding ID */
 300                 clrbits_le32(&mctl_com->cr, BIT(27));
 301         else if (readl(SUNXI_SIDC_BASE + 0x100) == 3)
 302                 setbits_le32(&mctl_com->cr, BIT(27));
 303
 304         if (para->clk > 408)
 305                 reg_val = 0xf00;
 306         else if (para->clk > 246)
 307                 reg_val = 0x1f00;
 308         else
 309                 reg_val = 0x3f00;
 310         clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
 311
 312         /* TODO: DDR4 */
 313         reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
 314         if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
 315                 reg_val |= MSTR_DEVICETYPE_LPDDR3;
 316         if (para->type == SUNXI_DRAM_TYPE_DDR3)
 317                 reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
 318         if (para->bus_full_width)
 319                 reg_val |= MSTR_BUSWIDTH_FULL;
 320         else
 321                 reg_val |= MSTR_BUSWIDTH_HALF;
 322         writel(reg_val | BIT(31), &mctl_ctl->mstr);
 323
 324         if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
 325                 reg_val = DCR_LPDDR3 | DCR_DDR8BANK;
 326         if (para->type == SUNXI_DRAM_TYPE_DDR3)
 327                 reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
 328         writel(reg_val | 0x400, &mctl_phy->dcr);
 329
 330         if (para->ranks == 2)
 331                 writel(0x0303, &mctl_ctl->odtmap);
 332         else
 333                 writel(0x0201, &mctl_ctl->odtmap);
 334
 335         /* TODO: DDR4 */
 336         if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
 337                 tmp = para->clk * 7 / 2000;
 338                 reg_val = 0x0400;
 339                 reg_val |= (tmp + 7) << 24;
 340                 reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
 341         } else if (para->type == SUNXI_DRAM_TYPE_DDR3) {
 342                 reg_val = 0x06000400;   /* TODO?: Use CL - CWL value in [7:0] */
 343         } else {
 344                 panic("Only (LP)DDR3 supported (type = %d)\n", para->type);
 345         }
 346         writel(reg_val, &mctl_ctl->odtcfg);
 347
 348         if (!para->bus_full_width) {
 349                 writel(0x0, &mctl_phy->dx[2].gcr[0]);
 350                 writel(0x0, &mctl_phy->dx[3].gcr[0]);
 351         }
 352 }
 353
 354 static void mctl_bit_delay_set(struct dram_para *para)
 355 {
 356         struct sunxi_mctl_phy_reg * const mctl_phy =
 357                         (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
 358         int i, j;
 359         u32 val;
 360
 361         for (i = 0; i < 4; i++) {
 362                 val = readl(&mctl_phy->dx[i].bdlr0);
 363                 for (j = 0; j < 4; j++)
 364                         val += para->dx_write_delays[i][j] << (j * 8);
 365                 writel(val, &mctl_phy->dx[i].bdlr0);
 366
 367                 val = readl(&mctl_phy->dx[i].bdlr1);
 368                 for (j = 0; j < 4; j++)
 369                         val += para->dx_write_delays[i][j + 4] << (j * 8);
 370                 writel(val, &mctl_phy->dx[i].bdlr1);
 371
 372                 val = readl(&mctl_phy->dx[i].bdlr2);
 373                 for (j = 0; j < 4; j++)
 374                         val += para->dx_write_delays[i][j + 8] << (j * 8);
 375                 writel(val, &mctl_phy->dx[i].bdlr2);
 376         }
 377         clrbits_le32(&mctl_phy->pgcr[0], BIT(26));
 378
 379         for (i = 0; i < 4; i++) {
 380                 val = readl(&mctl_phy->dx[i].bdlr3);
 381                 for (j = 0; j < 4; j++)
 382                         val += para->dx_read_delays[i][j] << (j * 8);
 383                 writel(val, &mctl_phy->dx[i].bdlr3);
 384
 385                 val = readl(&mctl_phy->dx[i].bdlr4);
 386                 for (j = 0; j < 4; j++)
 387                         val += para->dx_read_delays[i][j + 4] << (j * 8);
 388                 writel(val, &mctl_phy->dx[i].bdlr4);
 389
 390                 val = readl(&mctl_phy->dx[i].bdlr5);
 391                 for (j = 0; j < 4; j++)
 392                         val += para->dx_read_delays[i][j + 8] << (j * 8);
 393                 writel(val, &mctl_phy->dx[i].bdlr5);
 394
 395                 val = readl(&mctl_phy->dx[i].bdlr6);
 396                 val += (para->dx_read_delays[i][12] << 8) |
 397                        (para->dx_read_delays[i][13] << 16);
 398                 writel(val, &mctl_phy->dx[i].bdlr6);
 399         }
 400         setbits_le32(&mctl_phy->pgcr[0], BIT(26));
 401         udelay(1);
 402
 403         if (para->type != SUNXI_DRAM_TYPE_LPDDR3)
 404                 return;
 405
 406         for (i = 1; i < 14; i++) {
 407                 val = readl(&mctl_phy->acbdlr[i]);
 408                 val += 0x0a0a0a0a;
 409                 writel(val, &mctl_phy->acbdlr[i]);
 410         }
 411 }
 412
 413 static void mctl_channel_init(struct dram_para *para)
 414 {
 415         struct sunxi_mctl_com_reg * const mctl_com =
 416                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 417         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 418                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 419         struct sunxi_mctl_phy_reg * const mctl_phy =
 420                         (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
 421         int i;
 422         u32 val;
 423
 424         setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));
 425         setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));
 426         writel(0x2f05, &mctl_ctl->sched[0]);
 427         setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
 428         setbits_le32(&mctl_ctl->dfimisc, BIT(0));
 429         setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));
 430         clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0);
 431         /* TODO: non-LPDDR3 types */
 432         clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800));
 433         clrbits_le32(&mctl_phy->pgcr[6], BIT(0));
 434         clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220);
 435         /* TODO: VT compensation */
 436         clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060);
 437         clrbits_le32(&mctl_phy->vtcr[1], BIT(1));
 438
 439         for (i = 0; i < 4; i++)
 440                 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800);
 441         for (i = 0; i < 4; i++)
 442                 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555);
 443         for (i = 0; i < 4; i++)
 444                 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010);
 445
 446         udelay(100);
 447
 448         if (para->ranks == 2)
 449                 setbits_le32(&mctl_phy->dtcr[1], 0x30000);
 450         else
 451                 clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
 452
 453         if (sunxi_dram_is_lpddr(para->type))
 454                 clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
 455         if (para->ranks == 2) {
 456                 writel(0x00010001, &mctl_phy->rankidr);
 457                 writel(0x20000, &mctl_phy->odtcr);
 458         } else {
 459                 writel(0x0, &mctl_phy->rankidr);
 460                 writel(0x10000, &mctl_phy->odtcr);
 461         }
 462
 463         /* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */
 464         if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
 465                 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
 466         else
 467                 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000);
 468         if (para->clk <= 792) {
 469                 if (para->clk <= 672) {
 470                         if (para->clk <= 600)
 471                                 val = 0x300;
 472                         else
 473                                 val = 0x400;
 474                 } else {
 475                         val = 0x500;
 476                 }
 477         } else {
 478                 val = 0x600;
 479         }
 480         /* FIXME: NOT REVIEWED YET */
 481         clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val);
 482         clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff,
 483                         CONFIG_DRAM_ZQ & 0xff);
 484         clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);
 485         setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);
 486         setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);
 487         setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);
 488         clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);
 489         setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);
 490         setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);
 491         setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);
 492         if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
 493                 for (i = 1; i < 14; i++)
 494                         writel(0x06060606, &mctl_phy->acbdlr[i]);
 495         }
 496
 497         val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE |
 498               PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE;
 499         if (para->type == SUNXI_DRAM_TYPE_DDR3)
 500                 val |= PIR_DRAMRST | PIR_WL;
 501         mctl_phy_pir_init(val);
 502
 503         /* TODO: DDR4 types ? */
 504         for (i = 0; i < 4; i++)
 505                 writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
 506
 507         for (i = 0; i < 4; i++) {
 508                 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
 509                         val = 0x0;
 510                 else
 511                         val = 0xaaaa;
 512                 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val);
 513
 514                 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
 515                         val = 0x0;
 516                 else
 517                         val = 0x2020;
 518                 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val);
 519         }
 520
 521         mctl_bit_delay_set(para);
 522         udelay(1);
 523
 524         setbits_le32(&mctl_phy->pgcr[6], BIT(0));
 525         clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);
 526         for (i = 0; i < 4; i++)
 527                 clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
 528         udelay(10);
 529
 530         if (readl(&mctl_phy->pgsr[0]) & 0x400000)
 531         {
 532                 /* Check for single rank and optionally half DQ. */
 533                 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
 534                     (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
 535                         para->ranks = 1;
 536
 537                         if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
 538                             (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
 539                                 para->bus_full_width = 0;
 540
 541                         /* Restart DRAM initialization from scratch. */
 542                         mctl_core_init(para);
 543                         return;
 544                 }
 545
 546                 /*
 547                  * Check for dual rank and half DQ. NOTE: This combination
 548                  * is highly unlikely and was not tested. Condition is the
 549                  * same as in libdram, though.
 550                  */
 551                 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
 552                     (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
 553                         para->bus_full_width = 0;
 554
 555                         /* Restart DRAM initialization from scratch. */
 556                         mctl_core_init(para);
 557                         return;
 558                 }
 559
 560                 panic("This DRAM setup is currently not supported.\n");
 561         }
 562
 563         if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
 564                 /* Oops! There's something wrong! */
 565                 debug("PLL = %x\n", readl(0x3001010));
 566                 debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
 567                 for (i = 0; i < 4; i++)
 568                         debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
 569                 panic("Error while initializing DRAM PHY!\n");
 570         }
 571
 572         if (sunxi_dram_is_lpddr(para->type))
 573                 clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
 574         clrbits_le32(&mctl_phy->pgcr[1], 0x40);
 575         clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
 576         writel(1, &mctl_ctl->swctl);
 577         mctl_await_completion(&mctl_ctl->swstat, 1, 1);
 578         clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));
 579
 580         setbits_le32(&mctl_com->unk_0x014, BIT(31));
 581         writel(0xffffffff, &mctl_com->maer0);
 582         writel(0x7ff, &mctl_com->maer1);
 583         writel(0xffff, &mctl_com->maer2);
 584 }
 585
 586 static void mctl_auto_detect_dram_size(struct dram_para *para)
 587 {
 588         /* TODO: non-(LP)DDR3 */
 589         /* Detect rank number and half DQ by the code in mctl_channel_init. */
 590         mctl_core_init(para);
 591
 592         /* detect row address bits */
 593         para->cols = 8;
 594         para->rows = 18;
 595         mctl_core_init(para);
 596
 597         for (para->rows = 13; para->rows < 18; para->rows++) {
 598                 /* 8 banks, 8 bit per byte and 16/32 bit width */
 599                 if (mctl_mem_matches((1 << (para->rows + para->cols +
 600                                             4 + para->bus_full_width))))
 601                         break;
 602         }
 603
 604         /* detect column address bits */
 605         para->cols = 11;
 606         mctl_core_init(para);
 607
 608         for (para->cols = 8; para->cols < 11; para->cols++) {
 609                 /* 8 bits per byte and 16/32 bit width */
 610                 if (mctl_mem_matches(1 << (para->cols + 1 +
 611                                            para->bus_full_width)))
 612                         break;
 613         }
 614 }
 615
 616 unsigned long mctl_calc_size(struct dram_para *para)
 617 {
 618         u8 width = para->bus_full_width ? 4 : 2;
 619
 620         /* TODO: non-(LP)DDR3 */
 621
 622         /* 8 banks */
 623         return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
 624 }
 625
 626 #define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS                        \
 627         {{  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 628          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 629          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  4,  4,  0 },    \
 630          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 }}
 631 #define SUN50I_H6_LPDDR3_DX_READ_DELAYS                                 \
 632         {{  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
 633          {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
 634          {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
 635          {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 }}
 636
 637 #define SUN50I_H6_DDR3_DX_WRITE_DELAYS                          \
 638         {{  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 639          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 640          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 641          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 }}
 642 #define SUN50I_H6_DDR3_DX_READ_DELAYS                                   \
 643         {{  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 644          {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
 645          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
 646          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 }}
 647
 648 unsigned long sunxi_dram_init(void)
 649 {
 650         struct sunxi_mctl_com_reg * const mctl_com =
 651                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 652         struct dram_para para = {
 653                 .clk = CONFIG_DRAM_CLK,
 654                 .ranks = 2,
 655                 .cols = 11,
 656                 .rows = 14,
 657                 .bus_full_width = 1,
 658 #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
 659                 .type = SUNXI_DRAM_TYPE_LPDDR3,
 660                 .dx_read_delays  = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
 661                 .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
 662 #elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
 663                 .type = SUNXI_DRAM_TYPE_DDR3,
 664                 .dx_read_delays  = SUN50I_H6_DDR3_DX_READ_DELAYS,
 665                 .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
 666 #endif
 667         };
 668
 669         unsigned long size;
 670
 671         /* RES_CAL_CTRL_REG in BSP U-boot*/
 672         setbits_le32(0x7010310, BIT(8));
 673         clrbits_le32(0x7010318, 0x3f);
 674
 675         mctl_auto_detect_dram_size(&para);
 676
 677         mctl_core_init(&para);
 678
 679         size = mctl_calc_size(&para);
 680
 681         clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
 682
 683         mctl_set_master_priority();
 684
 685         return size;
 686 };