arch/arm/mach-sunxi/clock_sun8i_a83t.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * A83 specific clock code
   4  *
   5  * (C) Copyright 2007-2012
   6  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   7  * Tom Cubie <tangliang@allwinnertech.com>
   8  *
   9  * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
  10  */
  11
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/prcm.h>
  16 #include <asm/arch/sys_proto.h>
  17
  18 #ifdef CONFIG_SPL_BUILD
  19 void clock_init_safe(void)
  20 {
  21         struct sunxi_ccm_reg * const ccm =
  22                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  23
  24         clock_set_pll1(408000000);
  25         /* enable pll_hsic, default is 480M */
  26         writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg);
  27         writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg);
  28         while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {}
  29
  30         /* switch to default 24MHz before changing to hsic */
  31         writel(0x0, &ccm->cci400_cfg);
  32         sdelay(50);
  33         writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg);
  34         sdelay(100);
  35
  36         /* switch before changing pll6 */
  37         clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK,
  38                         AHB1_CLK_SRC_OSC24M);
  39         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  40         while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {}
  41
  42         writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
  43         writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset);
  44         writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg);
  45
  46         /* timestamp */
  47         writel(1, 0x01720000);
  48 }
  49 #endif
  50
  51 void clock_init_uart(void)
  52 {
  53         struct sunxi_ccm_reg *const ccm =
  54                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  55
  56         /* uart clock source is apb2 */
  57         writel(APB2_CLK_SRC_OSC24M|
  58                APB2_CLK_RATE_N_1|
  59                APB2_CLK_RATE_M(1),
  60                &ccm->apb2_div);
  61
  62         /* open the clock for uart */
  63         setbits_le32(&ccm->apb2_gate,
  64                      CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
  65                                        CONFIG_CONS_INDEX - 1));
  66
  67         /* deassert uart reset */
  68         setbits_le32(&ccm->apb2_reset_cfg,
  69                      1 << (APB2_RESET_UART_SHIFT +
  70                            CONFIG_CONS_INDEX - 1));
  71 }
  72
  73 #ifdef CONFIG_SPL_BUILD
  74 void clock_set_pll1(unsigned int clk)
  75 {
  76         struct sunxi_ccm_reg * const ccm =
  77                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  78         const int p = 0;
  79
  80         /* Switch to 24MHz clock while changing PLL1 */
  81         writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
  82                 AXI_DIV_2 << AXI1_DIV_SHIFT |
  83                 CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT |
  84                 CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT,
  85                &ccm->cpu_axi_cfg);
  86
  87         /* clk = 24*n/p, p is ignored if clock is >288MHz */
  88         writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
  89                 CCM_PLL1_CTRL_N(clk / 24000000),
  90                 &ccm->pll1_c0_cfg);
  91         while (!(readl(&ccm->pll_stable_status) & 0x01)) {}
  92
  93         writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
  94                 CCM_PLL1_CTRL_N(clk / (24000000)),
  95                 &ccm->pll1_c1_cfg);
  96         while (!(readl(&ccm->pll_stable_status) & 0x02)) {}
  97
  98         /* Switch CPU to PLL1 */
  99         writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
 100                 AXI_DIV_2 << AXI1_DIV_SHIFT |
 101                 CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT |
 102                 CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT,
 103                &ccm->cpu_axi_cfg);
 104 }
 105 #endif
 106
 107 void clock_set_pll5(unsigned int clk)
 108 {
 109         struct sunxi_ccm_reg * const ccm =
 110                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 111         unsigned int div1 = 0, div2 = 0;
 112
 113         /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */
 114         writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
 115                         CCM_PLL5_CTRL_N(clk / (24000000)) |
 116                         div2 << CCM_PLL5_DIV2_SHIFT |
 117                         div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg);
 118
 119         udelay(5500);
 120 }
 121
 122
 123 unsigned int clock_get_pll6(void)
 124 {
 125         struct sunxi_ccm_reg *const ccm =
 126                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 127
 128         uint32_t rval = readl(&ccm->pll6_cfg);
 129         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
 130         int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
 131                         CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
 132         int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
 133                         CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
 134         return 24000000 * n / div1 / div2;
 135 }