4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
52 bool "Allwinner sun6i internal P2WI controller"
54 If you say yes to this option, support will be included for the
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
57 The P2WI looks like an SMBus controller (which supports only byte
58 accesses), except that it only supports one slave device.
59 This interface is used to connect to specific PMIC devices (like the
65 Support for the PRCM (Power/Reset/Clock Management) unit available
69 bool "Sunxi AXP PMIC bus access helpers"
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
72 AXP family PMIC devices.
75 bool "Allwinner sunXi Reduced Serial Bus Driver"
77 Say y here to enable support for Allwinner's Reduced Serial Bus
78 (RSB) support. This controller is responsible for communicating
79 with various RSB based devices, such as AXP223, AXP8XX PMICs,
82 config SUNXI_SRAM_ADDRESS
84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85 default 0x20000 if MACH_SUN50I_H6
88 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89 with the first SRAM region being located at address 0.
90 Some newer SoCs map the boot ROM at address 0 instead and move the
91 SRAM to a different address.
93 config SUNXI_A64_TIMER_ERRATUM
96 # Note only one of these may be selected at a time! But hidden choices are
97 # not supported by Kconfig
98 config SUNXI_GEN_SUN4I
101 Select this for sunxi SoCs which have resets and clocks set up
102 as the original A10 (mach-sun4i).
104 config SUNXI_GEN_SUN6I
107 Select this for sunxi SoCs which have sun6i like periphery, like
108 separate ahb reset control registers, custom pmic bus, new style
114 Select this for sunxi SoCs which uses a DRAM controller like the
115 DesignWare controller used in H3, mainly SoCs after H3, which do
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
120 config SUNXI_DRAM_DW_16BIT
123 Select this for sunxi SoCs with DesignWare DRAM controller and
124 have only 16-bit memory buswidth.
126 config SUNXI_DRAM_DW_32BIT
129 Select this for sunxi SoCs with DesignWare DRAM controller with
130 32-bit memory buswidth.
133 config MACH_SUNXI_H3_H5
139 select SUNXI_DRAM_DW_32BIT
140 select SUNXI_GEN_SUN6I
143 # TODO: try out A80's 8GiB DRAM space
144 config SUNXI_DRAM_MAX_SIZE
146 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
150 prompt "Sunxi SoC Variant"
154 bool "sun4i (Allwinner A10)"
156 select ARM_CORTEX_CPU_IS_UP
159 select SUNXI_GEN_SUN4I
163 bool "sun5i (Allwinner A13)"
165 select ARM_CORTEX_CPU_IS_UP
168 select SUNXI_GEN_SUN4I
170 imply CONS_INDEX_2 if !DM_SERIAL
173 bool "sun6i (Allwinner A31)"
175 select CPU_V7_HAS_NONSEC
176 select CPU_V7_HAS_VIRT
177 select ARCH_SUPPORT_PSCI
182 select SUNXI_GEN_SUN6I
184 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
187 bool "sun7i (Allwinner A20)"
189 select CPU_V7_HAS_NONSEC
190 select CPU_V7_HAS_VIRT
191 select ARCH_SUPPORT_PSCI
194 select SUNXI_GEN_SUN4I
196 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
198 config MACH_SUN8I_A23
199 bool "sun8i (Allwinner A23)"
201 select CPU_V7_HAS_NONSEC
202 select CPU_V7_HAS_VIRT
203 select ARCH_SUPPORT_PSCI
204 select DRAM_SUN8I_A23
206 select SUNXI_GEN_SUN6I
208 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
209 imply CONS_INDEX_5 if !DM_SERIAL
211 config MACH_SUN8I_A33
212 bool "sun8i (Allwinner A33)"
214 select CPU_V7_HAS_NONSEC
215 select CPU_V7_HAS_VIRT
216 select ARCH_SUPPORT_PSCI
217 select DRAM_SUN8I_A33
219 select SUNXI_GEN_SUN6I
221 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
222 imply CONS_INDEX_5 if !DM_SERIAL
224 config MACH_SUN8I_A83T
225 bool "sun8i (Allwinner A83T)"
227 select DRAM_SUN8I_A83T
229 select SUNXI_GEN_SUN6I
230 select MMC_SUNXI_HAS_NEW_MODE
231 select MMC_SUNXI_HAS_MODE_SWITCH
235 bool "sun8i (Allwinner H3)"
237 select CPU_V7_HAS_NONSEC
238 select CPU_V7_HAS_VIRT
239 select ARCH_SUPPORT_PSCI
240 select MACH_SUNXI_H3_H5
241 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
243 config MACH_SUN8I_R40
244 bool "sun8i (Allwinner R40)"
246 select CPU_V7_HAS_NONSEC
247 select CPU_V7_HAS_VIRT
248 select ARCH_SUPPORT_PSCI
249 select SUNXI_GEN_SUN6I
252 select SUNXI_DRAM_DW_32BIT
254 config MACH_SUN8I_V3S
255 bool "sun8i (Allwinner V3s)"
257 select CPU_V7_HAS_NONSEC
258 select CPU_V7_HAS_VIRT
259 select ARCH_SUPPORT_PSCI
260 select SUNXI_GEN_SUN6I
262 select SUNXI_DRAM_DW_16BIT
264 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
267 bool "sun9i (Allwinner A80)"
271 select SUNXI_GEN_SUN6I
276 bool "sun50i (Allwinner A64)"
285 select SUNXI_GEN_SUN6I
286 select MMC_SUNXI_HAS_NEW_MODE
289 select SUNXI_DRAM_DW_32BIT
292 select SUNXI_A64_TIMER_ERRATUM
294 config MACH_SUN50I_H5
295 bool "sun50i (Allwinner H5)"
297 select MACH_SUNXI_H3_H5
301 config MACH_SUN50I_H6
302 bool "sun50i (Allwinner H6)"
308 select DRAM_SUN50I_H6
312 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
317 default y if MACH_SUN8I_A23
318 default y if MACH_SUN8I_A33
319 default y if MACH_SUN8I_A83T
320 default y if MACH_SUNXI_H3_H5
321 default y if MACH_SUN8I_R40
322 default y if MACH_SUN8I_V3S
324 config RESERVE_ALLWINNER_BOOT0_HEADER
325 bool "reserve space for Allwinner boot0 header"
326 select ENABLE_ARM_SOC_BOOT0_HOOK
328 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
329 filled with magic values post build. The Allwinner provided boot0
330 blob relies on this information to load and execute U-Boot.
331 Only needed on 64-bit Allwinner boards so far when using boot0.
333 config ARM_BOOT_HOOK_RMR
337 select ENABLE_ARM_SOC_BOOT0_HOOK
339 Insert some ARM32 code at the very beginning of the U-Boot binary
340 which uses an RMR register write to bring the core into AArch64 mode.
341 The very first instruction acts as a switch, since it's carefully
342 chosen to be a NOP in one mode and a branch in the other, so the
343 code would only be executed if not already in AArch64.
344 This allows both the SPL and the U-Boot proper to be entered in
345 either mode and switch to AArch64 if needed.
347 if SUNXI_DRAM_DW || DRAM_SUN50I_H6
348 config SUNXI_DRAM_DDR3
351 config SUNXI_DRAM_DDR2
354 config SUNXI_DRAM_LPDDR3
358 prompt "DRAM Type and Timing"
359 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
360 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
362 config SUNXI_DRAM_DDR3_1333
364 select SUNXI_DRAM_DDR3
365 depends on !MACH_SUN8I_V3S
367 This option is the original only supported memory type, which suits
368 many H3/H5/A64 boards available now.
370 config SUNXI_DRAM_LPDDR3_STOCK
371 bool "LPDDR3 with Allwinner stock configuration"
372 select SUNXI_DRAM_LPDDR3
374 This option is the LPDDR3 timing used by the stock boot0 by
377 config SUNXI_DRAM_H6_LPDDR3
378 bool "LPDDR3 DRAM chips on the H6 DRAM controller"
379 select SUNXI_DRAM_LPDDR3
380 depends on DRAM_SUN50I_H6
382 This option is the LPDDR3 timing used by the stock boot0 by
385 config SUNXI_DRAM_H6_DDR3_1333
386 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
387 select SUNXI_DRAM_DDR3
388 depends on DRAM_SUN50I_H6
390 This option is the DDR3 timing used by the boot0 on H6 TV boxes
391 which use a DDR3-1333 timing.
393 config SUNXI_DRAM_DDR2_V3S
394 bool "DDR2 found in V3s chip"
395 select SUNXI_DRAM_DDR2
396 depends on MACH_SUN8I_V3S
398 This option is only for the DDR2 memory chip which is co-packaged in
405 int "sunxi dram type"
406 depends on MACH_SUN8I_A83T
409 Set the dram type, 3: DDR3, 7: LPDDR3
412 int "sunxi dram clock speed"
413 default 792 if MACH_SUN9I
414 default 648 if MACH_SUN8I_R40
415 default 312 if MACH_SUN6I || MACH_SUN8I
416 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
418 default 672 if MACH_SUN50I
419 default 744 if MACH_SUN50I_H6
421 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
422 must be a multiple of 24. For the sun9i (A80), the tested values
423 (for DDR3-1600) are 312 to 792.
425 if MACH_SUN5I || MACH_SUN7I
427 int "sunxi mbus clock speed"
430 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
435 int "sunxi dram zq value"
436 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
437 MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
438 default 127 if MACH_SUN7I
439 default 14779 if MACH_SUN8I_V3S
440 default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
441 default 4145117 if MACH_SUN9I
442 default 3881915 if MACH_SUN50I
444 Set the dram zq value.
447 bool "sunxi dram odt enable"
448 default y if MACH_SUN8I_A23
449 default y if MACH_SUNXI_H3_H5
450 default y if MACH_SUN8I_R40
451 default y if MACH_SUN50I
452 default y if MACH_SUN50I_H6
454 Select this to enable dram odt (on die termination).
456 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
458 int "sunxi dram emr1 value"
459 default 0 if MACH_SUN4I
460 default 4 if MACH_SUN5I || MACH_SUN7I
462 Set the dram controller emr1 value.
465 hex "sunxi dram tpr3 value"
468 Set the dram controller tpr3 parameter. This parameter configures
469 the delay on the command lane and also phase shifts, which are
470 applied for sampling incoming read data. The default value 0
471 means that no phase/delay adjustments are necessary. Properly
472 configuring this parameter increases reliability at high DRAM
475 config DRAM_DQS_GATING_DELAY
476 hex "sunxi dram dqs_gating_delay value"
479 Set the dram controller dqs_gating_delay parmeter. Each byte
480 encodes the DQS gating delay for each byte lane. The delay
481 granularity is 1/4 cycle. For example, the value 0x05060606
482 means that the delay is 5 quarter-cycles for one lane (1.25
483 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
484 The default value 0 means autodetection. The results of hardware
485 autodetection are not very reliable and depend on the chip
486 temperature (sometimes producing different results on cold start
487 and warm reboot). But the accuracy of hardware autodetection
488 is usually good enough, unless running at really high DRAM
489 clocks speeds (up to 600MHz). If unsure, keep as 0.
492 prompt "sunxi dram timings"
493 default DRAM_TIMINGS_VENDOR_MAGIC
495 Select the timings of the DDR3 chips.
497 config DRAM_TIMINGS_VENDOR_MAGIC
498 bool "Magic vendor timings from Android"
500 The same DRAM timings as in the Allwinner boot0 bootloader.
502 config DRAM_TIMINGS_DDR3_1066F_1333H
503 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
505 Use the timings of the standard JEDEC DDR3-1066F speed bin for
506 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
507 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
508 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
509 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
510 that down binning to DDR3-1066F is supported (because DDR3-1066F
511 uses a bit faster timings than DDR3-1333H).
513 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
514 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
516 Use the timings of the slowest possible JEDEC speed bin for the
517 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
518 DDR3-800E, DDR3-1066G or DDR3-1333J.
525 config DRAM_ODT_CORRECTION
526 int "sunxi dram odt correction value"
529 Set the dram odt correction value (range -255 - 255). In allwinner
530 fex files, this option is found in bits 8-15 of the u32 odt_en variable
531 in the [dram] section. When bit 31 of the odt_en variable is set
532 then the correction is negative. Usually the value for this is 0.
536 default 1008000000 if MACH_SUN4I
537 default 1008000000 if MACH_SUN5I
538 default 1008000000 if MACH_SUN6I
539 default 912000000 if MACH_SUN7I
540 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
541 default 1008000000 if MACH_SUN8I
542 default 1008000000 if MACH_SUN9I
543 default 888000000 if MACH_SUN50I_H6
545 config SYS_CONFIG_NAME
546 default "sun4i" if MACH_SUN4I
547 default "sun5i" if MACH_SUN5I
548 default "sun6i" if MACH_SUN6I
549 default "sun7i" if MACH_SUN7I
550 default "sun8i" if MACH_SUN8I
551 default "sun9i" if MACH_SUN9I
552 default "sun50i" if MACH_SUN50I
553 default "sun50i" if MACH_SUN50I_H6
562 bool "UART0 on MicroSD breakout board"
565 Repurpose the SD card slot for getting access to the UART0 serial
566 console. Primarily useful only for low level u-boot debugging on
567 tablets, where normal UART0 is difficult to access and requires
568 device disassembly and/or soldering. As the SD card can't be used
569 at the same time, the system can be only booted in the FEL mode.
570 Only enable this if you really know what you are doing.
572 config OLD_SUNXI_KERNEL_COMPAT
573 bool "Enable workarounds for booting old kernels"
576 Set this to enable various workarounds for old kernels, this results in
577 sub-optimal settings for newer kernels, only enable if needed.
580 string "MAC power pin"
583 Set the pin used to power the MAC. This takes a string in the format
584 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
587 string "Card detect pin for mmc0"
588 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
591 Set the card detect pin for mmc0, leave empty to not use cd. This
592 takes a string in the format understood by sunxi_name_to_gpio, e.g.
593 PH1 for pin 1 of port H.
596 string "Card detect pin for mmc1"
599 See MMC0_CD_PIN help text.
602 string "Card detect pin for mmc2"
605 See MMC0_CD_PIN help text.
608 string "Card detect pin for mmc3"
611 See MMC0_CD_PIN help text.
614 string "Pins for mmc1"
617 Set the pins used for mmc1, when applicable. This takes a string in the
618 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
621 string "Pins for mmc2"
624 See MMC1_PINS help text.
627 string "Pins for mmc3"
630 See MMC1_PINS help text.
632 config MMC_SUNXI_SLOT_EXTRA
633 int "mmc extra slot number"
636 sunxi builds always enable mmc0, some boards also have a second sdcard
637 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
640 config INITIAL_USB_SCAN_DELAY
641 int "delay initial usb scan by x ms to allow builtin devices to init"
644 Some boards have on board usb devices which need longer than the
645 USB spec's 1 second to connect from board powerup. Set this config
646 option to a non 0 value to add an extra delay before the first usb
650 string "Vbus enable pin for usb0 (otg)"
653 Set the Vbus enable pin for usb0 (otg). This takes a string in the
654 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
657 string "Vbus detect pin for usb0 (otg)"
660 Set the Vbus detect pin for usb0 (otg). This takes a string in the
661 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
664 string "ID detect pin for usb0 (otg)"
667 Set the ID detect pin for usb0 (otg). This takes a string in the
668 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
671 string "Vbus enable pin for usb1 (ehci0)"
672 default "PH6" if MACH_SUN4I || MACH_SUN7I
673 default "PH27" if MACH_SUN6I
675 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
676 a string in the format understood by sunxi_name_to_gpio, e.g.
677 PH1 for pin 1 of port H.
680 string "Vbus enable pin for usb2 (ehci1)"
681 default "PH3" if MACH_SUN4I || MACH_SUN7I
682 default "PH24" if MACH_SUN6I
684 See USB1_VBUS_PIN help text.
687 string "Vbus enable pin for usb3 (ehci2)"
690 See USB1_VBUS_PIN help text.
693 bool "Enable I2C/TWI controller 0"
694 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
695 default n if MACH_SUN6I || MACH_SUN8I
698 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
699 its clock and setting up the bus. This is especially useful on devices
700 with slaves connected to the bus or with pins exposed through e.g. an
701 expansion port/header.
704 bool "Enable I2C/TWI controller 1"
708 See I2C0_ENABLE help text.
711 bool "Enable I2C/TWI controller 2"
715 See I2C0_ENABLE help text.
717 if MACH_SUN6I || MACH_SUN7I
719 bool "Enable I2C/TWI controller 3"
723 See I2C0_ENABLE help text.
728 bool "Enable the PRCM I2C/TWI controller"
729 # This is used for the pmic on H3
730 default y if SY8106A_POWER
733 Set this to y to enable the I2C controller which is part of the PRCM.
738 bool "Enable I2C/TWI controller 4"
742 See I2C0_ENABLE help text.
746 bool "Enable support for gpio-s on axp PMICs"
749 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
752 bool "Enable graphical uboot console on HDMI, LCD or VGA"
753 depends on !MACH_SUN8I_A83T
754 depends on !MACH_SUNXI_H3_H5
755 depends on !MACH_SUN8I_R40
756 depends on !MACH_SUN8I_V3S
757 depends on !MACH_SUN9I
758 depends on !MACH_SUN50I
759 depends on !MACH_SUN50I_H6
761 imply VIDEO_DT_SIMPLEFB
764 Say Y here to add support for using a cfb console on the HDMI, LCD
765 or VGA output found on most sunxi devices. See doc/README.video for
766 info on how to select the video output and mode.
769 bool "HDMI output support"
770 depends on VIDEO_SUNXI && !MACH_SUN8I
773 Say Y here to add support for outputting video over HDMI.
776 bool "VGA output support"
777 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
780 Say Y here to add support for outputting video over VGA.
782 config VIDEO_VGA_VIA_LCD
783 bool "VGA via LCD controller support"
784 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
787 Say Y here to add support for external DACs connected to the parallel
788 LCD interface driving a VGA connector, such as found on the
791 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
792 bool "Force sync active high for VGA via LCD controller support"
793 depends on VIDEO_VGA_VIA_LCD
796 Say Y here if you've a board which uses opendrain drivers for the vga
797 hsync and vsync signals. Opendrain drivers cannot generate steep enough
798 positive edges for a stable video output, so on boards with opendrain
799 drivers the sync signals must always be active high.
801 config VIDEO_VGA_EXTERNAL_DAC_EN
802 string "LCD panel power enable pin"
803 depends on VIDEO_VGA_VIA_LCD
806 Set the enable pin for the external VGA DAC. This takes a string in the
807 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
809 config VIDEO_COMPOSITE
810 bool "Composite video output support"
811 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
814 Say Y here to add support for outputting composite video.
816 config VIDEO_LCD_MODE
817 string "LCD panel timing details"
818 depends on VIDEO_SUNXI
821 LCD panel timing details string, leave empty if there is no LCD panel.
822 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
823 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
824 Also see: http://linux-sunxi.org/LCD
826 config VIDEO_LCD_DCLK_PHASE
827 int "LCD panel display clock phase"
828 depends on VIDEO_SUNXI || DM_VIDEO
831 Select LCD panel display clock phase shift, range 0-3.
833 config VIDEO_LCD_POWER
834 string "LCD panel power enable pin"
835 depends on VIDEO_SUNXI
838 Set the power enable pin for the LCD panel. This takes a string in the
839 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
841 config VIDEO_LCD_RESET
842 string "LCD panel reset pin"
843 depends on VIDEO_SUNXI
846 Set the reset pin for the LCD panel. This takes a string in the format
847 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
849 config VIDEO_LCD_BL_EN
850 string "LCD panel backlight enable pin"
851 depends on VIDEO_SUNXI
854 Set the backlight enable pin for the LCD panel. This takes a string in the
855 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
858 config VIDEO_LCD_BL_PWM
859 string "LCD panel backlight pwm pin"
860 depends on VIDEO_SUNXI
863 Set the backlight pwm pin for the LCD panel. This takes a string in the
864 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
866 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
867 bool "LCD panel backlight pwm is inverted"
868 depends on VIDEO_SUNXI
871 Set this if the backlight pwm output is active low.
873 config VIDEO_LCD_PANEL_I2C
874 bool "LCD panel needs to be configured via i2c"
875 depends on VIDEO_SUNXI
879 Say y here if the LCD panel needs to be configured via i2c. This
880 will add a bitbang i2c controller using gpios to talk to the LCD.
882 config VIDEO_LCD_PANEL_I2C_SDA
883 string "LCD panel i2c interface SDA pin"
884 depends on VIDEO_LCD_PANEL_I2C
887 Set the SDA pin for the LCD i2c interface. This takes a string in the
888 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
890 config VIDEO_LCD_PANEL_I2C_SCL
891 string "LCD panel i2c interface SCL pin"
892 depends on VIDEO_LCD_PANEL_I2C
895 Set the SCL pin for the LCD i2c interface. This takes a string in the
896 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
899 # Note only one of these may be selected at a time! But hidden choices are
900 # not supported by Kconfig
901 config VIDEO_LCD_IF_PARALLEL
904 config VIDEO_LCD_IF_LVDS
912 bool "Display Engine 2 video driver"
916 imply VIDEO_DT_SIMPLEFB
919 Say y here if you want to build DE2 video driver which is present on
920 newer SoCs. Currently only HDMI output is supported.
924 prompt "LCD panel support"
925 depends on VIDEO_SUNXI
927 Select which type of LCD panel to support.
929 config VIDEO_LCD_PANEL_PARALLEL
930 bool "Generic parallel interface LCD panel"
931 select VIDEO_LCD_IF_PARALLEL
933 config VIDEO_LCD_PANEL_LVDS
934 bool "Generic lvds interface LCD panel"
935 select VIDEO_LCD_IF_LVDS
937 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
938 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
939 select VIDEO_LCD_SSD2828
940 select VIDEO_LCD_IF_PARALLEL
942 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
944 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
945 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
946 select VIDEO_LCD_ANX9804
947 select VIDEO_LCD_IF_PARALLEL
948 select VIDEO_LCD_PANEL_I2C
950 Select this for eDP LCD panels with 4 lanes running at 1.62G,
951 connected via an ANX9804 bridge chip.
953 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
954 bool "Hitachi tx18d42vm LCD panel"
955 select VIDEO_LCD_HITACHI_TX18D42VM
956 select VIDEO_LCD_IF_LVDS
958 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
960 config VIDEO_LCD_TL059WV5C0
961 bool "tl059wv5c0 LCD panel"
962 select VIDEO_LCD_PANEL_I2C
963 select VIDEO_LCD_IF_PARALLEL
965 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
966 Aigo M60/M608/M606 tablets.
971 string "SATA power pin"
974 Set the pins used to power the SATA. This takes a string in the
975 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
979 int "GMAC Transmit Clock Delay Chain"
982 Set the GMAC Transmit Clock Delay Chain value.
984 config SPL_STACK_R_ADDR
985 default 0x4fe00000 if MACH_SUN4I
986 default 0x4fe00000 if MACH_SUN5I
987 default 0x4fe00000 if MACH_SUN6I
988 default 0x4fe00000 if MACH_SUN7I
989 default 0x4fe00000 if MACH_SUN8I
990 default 0x2fe00000 if MACH_SUN9I
991 default 0x4fe00000 if MACH_SUN50I
992 default 0x4fe00000 if MACH_SUN50I_H6
995 bool "Support for SPI Flash on Allwinner SoCs in SPL"
996 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
998 Enable support for SPI Flash. This option allows SPL to read from
999 sunxi SPI Flash. It uses the same method as the boot ROM, so does
1000 not need any extra configuration.
1002 config PINE64_DT_SELECTION
1003 bool "Enable Pine64 device tree selection code"
1004 depends on MACH_SUN50I
1006 The original Pine A64 and Pine A64+ are similar but different
1007 boards and can be differed by the DRAM size. Pine A64 has
1008 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1009 option, the device tree selection code specific to Pine64 which
1010 utilizes the DRAM size will be enabled.