arch/arm/mach-stm32mp/psci.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <config.h>
   7 #include <common.h>
   8 #include <asm/armv7.h>
   9 #include <asm/gic.h>
  10 #include <asm/io.h>
  11 #include <asm/psci.h>
  12 #include <asm/secure.h>
  13
  14 #define BOOT_API_A7_CORE0_MAGIC_NUMBER  0xCA7FACE0
  15 #define BOOT_API_A7_CORE1_MAGIC_NUMBER  0xCA7FACE1
  16
  17 #define MPIDR_AFF0                      GENMASK(7, 0)
  18
  19 #define RCC_MP_GRSTCSETR                (STM32_RCC_BASE + 0x0404)
  20 #define RCC_MP_GRSTCSETR_MPUP1RST       BIT(5)
  21 #define RCC_MP_GRSTCSETR_MPUP0RST       BIT(4)
  22 #define RCC_MP_GRSTCSETR_MPSYSRST       BIT(0)
  23
  24 #define STM32MP1_PSCI_NR_CPUS           2
  25 #if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
  26 #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
  27 #endif
  28
  29 u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = {
  30          PSCI_AFFINITY_LEVEL_ON,
  31          PSCI_AFFINITY_LEVEL_OFF};
  32
  33 void __secure psci_set_state(int cpu, u8 state)
  34 {
  35         psci_state[cpu] = state;
  36         dsb();
  37         isb();
  38 }
  39
  40 static u32 __secure stm32mp_get_gicd_base_address(void)
  41 {
  42         u32 periphbase;
  43
  44         /* get the GIC base address from the CBAR register */
  45         asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
  46
  47         return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
  48 }
  49
  50 static void __secure stm32mp_smp_kick_all_cpus(void)
  51 {
  52         u32 gic_dist_addr;
  53
  54         gic_dist_addr = stm32mp_get_gicd_base_address();
  55
  56         /* kick all CPUs (except this one) by writing to GICD_SGIR */
  57         writel(1U << 24, gic_dist_addr + GICD_SGIR);
  58 }
  59
  60 void __secure psci_arch_cpu_entry(void)
  61 {
  62         u32 cpu = psci_get_cpu_id();
  63
  64         psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
  65 }
  66
  67 int __secure psci_features(u32 function_id, u32 psci_fid)
  68 {
  69         switch (psci_fid) {
  70         case ARM_PSCI_0_2_FN_PSCI_VERSION:
  71         case ARM_PSCI_0_2_FN_CPU_OFF:
  72         case ARM_PSCI_0_2_FN_CPU_ON:
  73         case ARM_PSCI_0_2_FN_AFFINITY_INFO:
  74         case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
  75         case ARM_PSCI_0_2_FN_SYSTEM_OFF:
  76         case ARM_PSCI_0_2_FN_SYSTEM_RESET:
  77                 return 0x0;
  78         }
  79         return ARM_PSCI_RET_NI;
  80 }
  81
  82 unsigned int __secure psci_version(u32 function_id)
  83 {
  84         return ARM_PSCI_VER_1_0;
  85 }
  86
  87 int __secure psci_affinity_info(u32 function_id, u32 target_affinity,
  88                                 u32  lowest_affinity_level)
  89 {
  90         u32 cpu = target_affinity & MPIDR_AFF0;
  91
  92         if (lowest_affinity_level > 0)
  93                 return ARM_PSCI_RET_INVAL;
  94
  95         if (target_affinity & ~MPIDR_AFF0)
  96                 return ARM_PSCI_RET_INVAL;
  97
  98         if (cpu >= STM32MP1_PSCI_NR_CPUS)
  99                 return ARM_PSCI_RET_INVAL;
 100
 101         return psci_state[cpu];
 102 }
 103
 104 int __secure psci_migrate_info_type(u32 function_id)
 105 {
 106         /*
 107          * in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
 108          * return 2 = Trusted OS is either not present or does not require
 109          * migration, system of this type does not require the caller
 110          * to use the MIGRATE function.
 111          * MIGRATE function calls return NOT_SUPPORTED.
 112          */
 113         return 2;
 114 }
 115
 116 int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
 117                          u32 context_id)
 118 {
 119         u32 cpu = target_cpu & MPIDR_AFF0;
 120
 121         if (target_cpu & ~MPIDR_AFF0)
 122                 return ARM_PSCI_RET_INVAL;
 123
 124         if (cpu >= STM32MP1_PSCI_NR_CPUS)
 125                 return ARM_PSCI_RET_INVAL;
 126
 127         if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
 128                 return ARM_PSCI_RET_ALREADY_ON;
 129
 130         /* store target PC and context id*/
 131         psci_save(cpu, pc, context_id);
 132
 133         /* write entrypoint in backup RAM register */
 134         writel((u32)&psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS);
 135         psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
 136
 137         /* write magic number in backup register */
 138         if (cpu == 0x01)
 139                 writel(BOOT_API_A7_CORE1_MAGIC_NUMBER,
 140                        TAMP_BACKUP_MAGIC_NUMBER);
 141         else
 142                 writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
 143                        TAMP_BACKUP_MAGIC_NUMBER);
 144
 145         stm32mp_smp_kick_all_cpus();
 146
 147         return ARM_PSCI_RET_SUCCESS;
 148 }
 149
 150 int __secure psci_cpu_off(u32 function_id)
 151 {
 152         u32 cpu;
 153
 154         cpu = psci_get_cpu_id();
 155
 156         psci_cpu_off_common();
 157         psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
 158
 159         /* reset core: wfi is managed by BootRom */
 160         if (cpu == 0x01)
 161                 writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR);
 162         else
 163                 writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR);
 164
 165         /* just waiting reset */
 166         while (1)
 167                 wfi();
 168 }
 169
 170 void __secure psci_system_reset(u32 function_id)
 171 {
 172         /* System reset */
 173         writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR);
 174         /* just waiting reset */
 175         while (1)
 176                 wfi();
 177 }
 178
 179 void __secure psci_system_off(u32 function_id)
 180 {
 181         /* System Off is not managed, waiting user power off
 182          * TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF
 183          */
 184         while (1)
 185                 wfi();
 186 }