1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
10 * Peripheral memory map
11 * only address used before device tree parsing
13 #define STM32_RCC_BASE 0x50000000
14 #define STM32_PWR_BASE 0x50001000
15 #define STM32_DBGMCU_BASE 0x50081000
16 #define STM32_TZC_BASE 0x5C006000
17 #define STM32_ETZPC_BASE 0x5C007000
18 #define STM32_STGEN_BASE 0x5C008000
19 #define STM32_TAMP_BASE 0x5C00A000
21 #define STM32_USART1_BASE 0x5C000000
22 #define STM32_USART2_BASE 0x4000E000
23 #define STM32_USART3_BASE 0x4000F000
24 #define STM32_UART4_BASE 0x40010000
25 #define STM32_UART5_BASE 0x40011000
26 #define STM32_USART6_BASE 0x44003000
27 #define STM32_UART7_BASE 0x40018000
28 #define STM32_UART8_BASE 0x40019000
30 #define STM32_SYSRAM_BASE 0x2FFC0000
31 #define STM32_SYSRAM_SIZE SZ_256K
33 #define STM32_DDR_BASE 0xC0000000
34 #define STM32_DDR_SIZE SZ_1G
37 /* enumerated used to identify the SYSCON driver instance */
39 STM32MP_SYSCON_UNKNOWN,
40 STM32MP_SYSCON_SYSCFG,
44 * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
45 * - boot device = bit 8:4
46 * - boot instance = bit 3:0
48 #define BOOT_TYPE_MASK 0xF0
49 #define BOOT_TYPE_SHIFT 4
50 #define BOOT_INSTANCE_MASK 0x0F
51 #define BOOT_INSTANCE_SHIFT 0
55 BOOT_FLASH_SD_1 = 0x11,
56 BOOT_FLASH_SD_2 = 0x12,
57 BOOT_FLASH_SD_3 = 0x13,
59 BOOT_FLASH_EMMC = 0x20,
60 BOOT_FLASH_EMMC_1 = 0x21,
61 BOOT_FLASH_EMMC_2 = 0x22,
62 BOOT_FLASH_EMMC_3 = 0x23,
64 BOOT_FLASH_NAND = 0x30,
65 BOOT_FLASH_NAND_FMC = 0x31,
67 BOOT_FLASH_NOR = 0x40,
68 BOOT_FLASH_NOR_QSPI = 0x41,
70 BOOT_SERIAL_UART = 0x50,
71 BOOT_SERIAL_UART_1 = 0x51,
72 BOOT_SERIAL_UART_2 = 0x52,
73 BOOT_SERIAL_UART_3 = 0x53,
74 BOOT_SERIAL_UART_4 = 0x54,
75 BOOT_SERIAL_UART_5 = 0x55,
76 BOOT_SERIAL_UART_6 = 0x56,
77 BOOT_SERIAL_UART_7 = 0x57,
78 BOOT_SERIAL_UART_8 = 0x58,
80 BOOT_SERIAL_USB = 0x60,
81 BOOT_SERIAL_USB_OTG = 0x62,
85 #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
86 #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
87 #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
88 #define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17)
89 #define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18)
90 #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20)
91 #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21)
93 #define TAMP_COPRO_STATE_OFF 0
94 #define TAMP_COPRO_STATE_INIT 1
95 #define TAMP_COPRO_STATE_CRUN 2
96 #define TAMP_COPRO_STATE_CSTOP 3
97 #define TAMP_COPRO_STATE_STANDBY 4
98 #define TAMP_COPRO_STATE_CRASH 5
100 #define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
101 #define TAMP_BOOT_MODE_SHIFT 8
102 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
103 #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
104 #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
105 #define TAMP_BOOT_DEBUG_ON BIT(16)
107 enum forced_boot_mode {
109 BOOT_FASTBOOT = 0x01,
110 BOOT_RECOVERY = 0x02,
111 BOOT_STM32PROG = 0x03,
112 BOOT_UMS_MMC0 = 0x10,
113 BOOT_UMS_MMC1 = 0x11,
114 BOOT_UMS_MMC2 = 0x12,
117 /* offset used for BSEC driver: misc_read and misc_write */
118 #define STM32_BSEC_SHADOW_OFFSET 0x0
119 #define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4)
120 #define STM32_BSEC_OTP_OFFSET 0x80000000
121 #define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4)
122 #define STM32_BSEC_LOCK_OFFSET 0xC0000000
123 #define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4)
126 #define BSEC_OTP_RPN 1
127 #define BSEC_OTP_SERIAL 13
128 #define BSEC_OTP_PKG 16
129 #define BSEC_OTP_MAC 57
130 #define BSEC_OTP_BOARD 59
132 #endif /* __ASSEMBLY__*/
133 #endif /* _MACH_STM32_H_ */