arch/arm/mach-stm32mp/include/mach/stm32.h

   1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #ifndef _MACH_STM32_H_
   7 #define _MACH_STM32_H_
   8
   9 /*
  10  * Peripheral memory map
  11  * only address used before device tree parsing
  12  */
  13 #define STM32_RCC_BASE                  0x50000000
  14 #define STM32_PWR_BASE                  0x50001000
  15 #define STM32_DBGMCU_BASE               0x50081000
  16 #define STM32_TZC_BASE                  0x5C006000
  17 #define STM32_ETZPC_BASE                0x5C007000
  18 #define STM32_TAMP_BASE                 0x5C00A000
  19
  20 #define STM32_SYSRAM_BASE               0x2FFC0000
  21 #define STM32_SYSRAM_SIZE               SZ_256K
  22
  23 #define STM32_DDR_BASE                  0xC0000000
  24 #define STM32_DDR_SIZE                  SZ_1G
  25
  26 #ifndef __ASSEMBLY__
  27 /* enumerated used to identify the SYSCON driver instance */
  28 enum {
  29         STM32MP_SYSCON_UNKNOWN,
  30         STM32MP_SYSCON_STGEN,
  31 };
  32
  33 /*
  34  * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
  35  * - boot device = bit 8:4
  36  * - boot instance = bit 3:0
  37  */
  38 #define BOOT_TYPE_MASK          0xF0
  39 #define BOOT_TYPE_SHIFT         4
  40 #define BOOT_INSTANCE_MASK      0x0F
  41 #define BOOT_INSTANCE_SHIFT     0
  42
  43 enum boot_device {
  44         BOOT_FLASH_SD = 0x10,
  45         BOOT_FLASH_SD_1 = 0x11,
  46         BOOT_FLASH_SD_2 = 0x12,
  47         BOOT_FLASH_SD_3 = 0x13,
  48
  49         BOOT_FLASH_EMMC = 0x20,
  50         BOOT_FLASH_EMMC_1 = 0x21,
  51         BOOT_FLASH_EMMC_2 = 0x22,
  52         BOOT_FLASH_EMMC_3 = 0x23,
  53
  54         BOOT_FLASH_NAND = 0x30,
  55         BOOT_FLASH_NAND_FMC = 0x31,
  56
  57         BOOT_FLASH_NOR = 0x40,
  58         BOOT_FLASH_NOR_QSPI = 0x41,
  59
  60         BOOT_SERIAL_UART = 0x50,
  61         BOOT_SERIAL_UART_1 = 0x51,
  62         BOOT_SERIAL_UART_2 = 0x52,
  63         BOOT_SERIAL_UART_3 = 0x53,
  64         BOOT_SERIAL_UART_4 = 0x54,
  65         BOOT_SERIAL_UART_5 = 0x55,
  66         BOOT_SERIAL_UART_6 = 0x56,
  67         BOOT_SERIAL_UART_7 = 0x57,
  68         BOOT_SERIAL_UART_8 = 0x58,
  69
  70         BOOT_SERIAL_USB = 0x60,
  71         BOOT_SERIAL_USB_OTG = 0x62,
  72 };
  73
  74 /* TAMP registers */
  75 #define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
  76 #define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
  77
  78 #define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
  79 #define TAMP_BOOT_MODE_SHIFT            8
  80 #define TAMP_BOOT_DEVICE_MASK           GENMASK(7, 4)
  81 #define TAMP_BOOT_INSTANCE_MASK         GENMASK(3, 0)
  82
  83 #endif /* __ASSEMBLY__*/
  84 #endif /* _MACH_STM32_H_ */