arch/arm/mach-stm32mp/fdt.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <fdt_support.h>
   8 #include <asm/arch/sys_proto.h>
   9 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
  10 #include <linux/io.h>
  11
  12 #define ETZPC_DECPROT(n)        (STM32_ETZPC_BASE + 0x10 + 4 * (n))
  13 #define ETZPC_DECPROT_NB        6
  14
  15 #define DECPROT_MASK            0x03
  16 #define NB_PROT_PER_REG         0x10
  17 #define DECPROT_NB_BITS         2
  18
  19 #define DECPROT_SECURED         0x00
  20 #define DECPROT_WRITE_SECURE    0x01
  21 #define DECPROT_MCU_ISOLATION   0x02
  22 #define DECPROT_NON_SECURED     0x03
  23
  24 #define ETZPC_RESERVED          0xffffffff
  25
  26 #define STM32_FDCAN_BASE        0x4400e000
  27 #define STM32_CRYP2_BASE        0x4c005000
  28 #define STM32_CRYP1_BASE        0x54001000
  29 #define STM32_GPU_BASE          0x59000000
  30 #define STM32_DSI_BASE          0x5a000000
  31
  32 static const u32 stm32mp1_ip_addr[] = {
  33         0x5c008000,     /* 00 stgenc */
  34         0x54000000,     /* 01 bkpsram */
  35         0x5c003000,     /* 02 iwdg1 */
  36         0x5c000000,     /* 03 usart1 */
  37         0x5c001000,     /* 04 spi6 */
  38         0x5c002000,     /* 05 i2c4 */
  39         ETZPC_RESERVED, /* 06 reserved */
  40         0x54003000,     /* 07 rng1 */
  41         0x54002000,     /* 08 hash1 */
  42         STM32_CRYP1_BASE,       /* 09 cryp1 */
  43         0x5a003000,     /* 0A ddrctrl */
  44         0x5a004000,     /* 0B ddrphyc */
  45         0x5c009000,     /* 0C i2c6 */
  46         ETZPC_RESERVED, /* 0D reserved */
  47         ETZPC_RESERVED, /* 0E reserved */
  48         ETZPC_RESERVED, /* 0F reserved */
  49         0x40000000,     /* 10 tim2 */
  50         0x40001000,     /* 11 tim3 */
  51         0x40002000,     /* 12 tim4 */
  52         0x40003000,     /* 13 tim5 */
  53         0x40004000,     /* 14 tim6 */
  54         0x40005000,     /* 15 tim7 */
  55         0x40006000,     /* 16 tim12 */
  56         0x40007000,     /* 17 tim13 */
  57         0x40008000,     /* 18 tim14 */
  58         0x40009000,     /* 19 lptim1 */
  59         0x4000a000,     /* 1A wwdg1 */
  60         0x4000b000,     /* 1B spi2 */
  61         0x4000c000,     /* 1C spi3 */
  62         0x4000d000,     /* 1D spdifrx */
  63         0x4000e000,     /* 1E usart2 */
  64         0x4000f000,     /* 1F usart3 */
  65         0x40010000,     /* 20 uart4 */
  66         0x40011000,     /* 21 uart5 */
  67         0x40012000,     /* 22 i2c1 */
  68         0x40013000,     /* 23 i2c2 */
  69         0x40014000,     /* 24 i2c3 */
  70         0x40015000,     /* 25 i2c5 */
  71         0x40016000,     /* 26 cec */
  72         0x40017000,     /* 27 dac */
  73         0x40018000,     /* 28 uart7 */
  74         0x40019000,     /* 29 uart8 */
  75         ETZPC_RESERVED, /* 2A reserved */
  76         ETZPC_RESERVED, /* 2B reserved */
  77         0x4001c000,     /* 2C mdios */
  78         ETZPC_RESERVED, /* 2D reserved */
  79         ETZPC_RESERVED, /* 2E reserved */
  80         ETZPC_RESERVED, /* 2F reserved */
  81         0x44000000,     /* 30 tim1 */
  82         0x44001000,     /* 31 tim8 */
  83         ETZPC_RESERVED, /* 32 reserved */
  84         0x44003000,     /* 33 usart6 */
  85         0x44004000,     /* 34 spi1 */
  86         0x44005000,     /* 35 spi4 */
  87         0x44006000,     /* 36 tim15 */
  88         0x44007000,     /* 37 tim16 */
  89         0x44008000,     /* 38 tim17 */
  90         0x44009000,     /* 39 spi5 */
  91         0x4400a000,     /* 3A sai1 */
  92         0x4400b000,     /* 3B sai2 */
  93         0x4400c000,     /* 3C sai3 */
  94         0x4400d000,     /* 3D dfsdm */
  95         STM32_FDCAN_BASE,       /* 3E tt_fdcan */
  96         ETZPC_RESERVED, /* 3F reserved */
  97         0x50021000,     /* 40 lptim2 */
  98         0x50022000,     /* 41 lptim3 */
  99         0x50023000,     /* 42 lptim4 */
 100         0x50024000,     /* 43 lptim5 */
 101         0x50027000,     /* 44 sai4 */
 102         0x50025000,     /* 45 vrefbuf */
 103         0x4c006000,     /* 46 dcmi */
 104         0x4c004000,     /* 47 crc2 */
 105         0x48003000,     /* 48 adc */
 106         0x4c002000,     /* 49 hash2 */
 107         0x4c003000,     /* 4A rng2 */
 108         STM32_CRYP2_BASE,       /* 4B cryp2 */
 109         ETZPC_RESERVED, /* 4C reserved */
 110         ETZPC_RESERVED, /* 4D reserved */
 111         ETZPC_RESERVED, /* 4E reserved */
 112         ETZPC_RESERVED, /* 4F reserved */
 113         ETZPC_RESERVED, /* 50 sram1 */
 114         ETZPC_RESERVED, /* 51 sram2 */
 115         ETZPC_RESERVED, /* 52 sram3 */
 116         ETZPC_RESERVED, /* 53 sram4 */
 117         ETZPC_RESERVED, /* 54 retram */
 118         0x49000000,     /* 55 otg */
 119         0x48004000,     /* 56 sdmmc3 */
 120         0x48005000,     /* 57 dlybsd3 */
 121         0x48000000,     /* 58 dma1 */
 122         0x48001000,     /* 59 dma2 */
 123         0x48002000,     /* 5A dmamux */
 124         0x58002000,     /* 5B fmc */
 125         0x58003000,     /* 5C qspi */
 126         0x58004000,     /* 5D dlybq */
 127         0x5800a000,     /* 5E eth */
 128         ETZPC_RESERVED, /* 5F reserved */
 129 };
 130
 131 /* fdt helper */
 132 static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
 133 {
 134         int node;
 135         fdt_addr_t regs;
 136
 137         for (node = fdt_first_subnode(fdt, offset);
 138              node >= 0;
 139              node = fdt_next_subnode(fdt, node)) {
 140                 regs = fdtdec_get_addr(fdt, node, "reg");
 141                 if (addr == regs) {
 142                         if (fdtdec_get_is_enabled(fdt, node)) {
 143                                 fdt_status_disabled(fdt, node);
 144
 145                                 return true;
 146                         }
 147                         return false;
 148                 }
 149         }
 150
 151         return false;
 152 }
 153
 154 static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
 155 {
 156         const u32 *array;
 157         int array_size, i;
 158         int offset, shift;
 159         u32 addr, status, decprot[ETZPC_DECPROT_NB];
 160
 161         array = stm32mp1_ip_addr;
 162         array_size = ARRAY_SIZE(stm32mp1_ip_addr);
 163
 164         for (i = 0; i < ETZPC_DECPROT_NB; i++)
 165                 decprot[i] = readl(ETZPC_DECPROT(i));
 166
 167         for (i = 0; i < array_size; i++) {
 168                 offset = i / NB_PROT_PER_REG;
 169                 shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
 170                 status = (decprot[offset] >> shift) & DECPROT_MASK;
 171                 addr = array[i];
 172
 173                 debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
 174
 175                 if (addr == ETZPC_RESERVED ||
 176                     status == DECPROT_NON_SECURED)
 177                         continue;
 178
 179                 if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
 180                         printf("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
 181                                addr, i, status);
 182         }
 183
 184         return 0;
 185 }
 186
 187 /* deactivate all the cpu except core 0 */
 188 static void stm32_fdt_fixup_cpu(void *blob, char *name)
 189 {
 190         int off;
 191         u32 reg;
 192
 193         off = fdt_path_offset(blob, "/cpus");
 194         if (off < 0) {
 195                 printf("%s: couldn't find /cpus node\n", __func__);
 196                 return;
 197         }
 198
 199         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 200         while (off != -FDT_ERR_NOTFOUND) {
 201                 reg = fdtdec_get_addr(blob, off, "reg");
 202                 if (reg != 0) {
 203                         fdt_del_node(blob, off);
 204                         printf("FDT: cpu %d node remove for %s\n", reg, name);
 205                         /* after delete we can't trust the offsets anymore */
 206                         off = -1;
 207                 }
 208                 off = fdt_node_offset_by_prop_value(blob, off,
 209                                                     "device_type", "cpu", 4);
 210         }
 211 }
 212
 213 static void stm32_fdt_disable(void *fdt, int offset, u32 addr,
 214                               const char *string, const char *name)
 215 {
 216         if (fdt_disable_subnode_by_address(fdt, offset, addr))
 217                 printf("FDT: %s@%08x node disabled for %s\n",
 218                        string, addr, name);
 219 }
 220
 221 /*
 222  * This function is called right before the kernel is booted. "blob" is the
 223  * device tree that will be passed to the kernel.
 224  */
 225 int ft_system_setup(void *blob, bd_t *bd)
 226 {
 227         int ret = 0;
 228         int soc;
 229         u32 pkg, cpu;
 230         char name[SOC_NAME_SIZE];
 231
 232         soc = fdt_path_offset(blob, "/soc");
 233         if (soc < 0)
 234                 return soc;
 235
 236         if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
 237                 ret = stm32_fdt_fixup_etzpc(blob, soc);
 238                 if (ret)
 239                         return ret;
 240         }
 241
 242         /* MPUs Part Numbers and name*/
 243         cpu = get_cpu_type();
 244         get_soc_name(name);
 245
 246         switch (cpu) {
 247         case CPU_STM32MP151Fxx:
 248         case CPU_STM32MP151Dxx:
 249         case CPU_STM32MP151Cxx:
 250         case CPU_STM32MP151Axx:
 251                 stm32_fdt_fixup_cpu(blob, name);
 252                 /* after cpu delete we can't trust the soc offsets anymore */
 253                 soc = fdt_path_offset(blob, "/soc");
 254                 stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
 255                 /* fall through */
 256         case CPU_STM32MP153Fxx:
 257         case CPU_STM32MP153Dxx:
 258         case CPU_STM32MP153Cxx:
 259         case CPU_STM32MP153Axx:
 260                 stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
 261                 stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name);
 262                 break;
 263         default:
 264                 break;
 265         }
 266
 267         switch (cpu) {
 268         case CPU_STM32MP157Dxx:
 269         case CPU_STM32MP157Axx:
 270         case CPU_STM32MP153Dxx:
 271         case CPU_STM32MP153Axx:
 272         case CPU_STM32MP151Dxx:
 273         case CPU_STM32MP151Axx:
 274                 stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name);
 275                 stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name);
 276                 break;
 277         default:
 278                 break;
 279         }
 280
 281         switch (get_cpu_package()) {
 282         case PKG_AA_LBGA448:
 283                 pkg = STM32MP_PKG_AA;
 284                 break;
 285         case PKG_AB_LBGA354:
 286                 pkg = STM32MP_PKG_AB;
 287                 break;
 288         case PKG_AC_TFBGA361:
 289                 pkg = STM32MP_PKG_AC;
 290                 break;
 291         case PKG_AD_TFBGA257:
 292                 pkg = STM32MP_PKG_AD;
 293                 break;
 294         default:
 295                 pkg = 0;
 296                 break;
 297         }
 298         if (pkg) {
 299                 do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
 300                                        "st,package", pkg, false);
 301                 do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
 302                                        "st,package", pkg, false);
 303         }
 304
 305         return ret;
 306 }