arch/arm/mach-socfpga/spl_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <asm/io.h>
   8 #include <asm/u-boot.h>
   9 #include <asm/utils.h>
  10 #include <common.h>
  11 #include <debug_uart.h>
  12 #include <image.h>
  13 #include <spl.h>
  14 #include <asm/arch/clock_manager.h>
  15 #include <asm/arch/firewall_s10.h>
  16 #include <asm/arch/mailbox_s10.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/arch/reset_manager.h>
  19 #include <asm/arch/system_manager.h>
  20 #include <watchdog.h>
  21 #include <dm/uclass.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 u32 spl_boot_device(void)
  26 {
  27         /* TODO: Get from SDM or handoff */
  28         return BOOT_DEVICE_MMC1;
  29 }
  30
  31 #ifdef CONFIG_SPL_MMC_SUPPORT
  32 u32 spl_boot_mode(const u32 boot_device)
  33 {
  34 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  35         return MMCSD_MODE_FS;
  36 #else
  37         return MMCSD_MODE_RAW;
  38 #endif
  39 }
  40 #endif
  41
  42 void spl_disable_firewall_l4_per(void)
  43 {
  44         const struct socfpga_firwall_l4_per *firwall_l4_per_base =
  45                 (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
  46         u32 i;
  47         const u32 *addr[] = {
  48                         &firwall_l4_per_base->nand,
  49                         &firwall_l4_per_base->nand_data,
  50                         &firwall_l4_per_base->usb0,
  51                         &firwall_l4_per_base->usb1,
  52                         &firwall_l4_per_base->spim0,
  53                         &firwall_l4_per_base->spim1,
  54                         &firwall_l4_per_base->emac0,
  55                         &firwall_l4_per_base->emac1,
  56                         &firwall_l4_per_base->emac2,
  57                         &firwall_l4_per_base->sdmmc,
  58                         &firwall_l4_per_base->gpio0,
  59                         &firwall_l4_per_base->gpio1,
  60                         &firwall_l4_per_base->i2c0,
  61                         &firwall_l4_per_base->i2c1,
  62                         &firwall_l4_per_base->i2c2,
  63                         &firwall_l4_per_base->i2c3,
  64                         &firwall_l4_per_base->i2c4,
  65                         &firwall_l4_per_base->timer0,
  66                         &firwall_l4_per_base->timer1,
  67                         &firwall_l4_per_base->uart0,
  68                         &firwall_l4_per_base->uart1
  69                         };
  70
  71         /*
  72          * The following lines of code will enable non-secure access
  73          * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
  74          * is needed as most OS run in non-secure mode. Thus we need to
  75          * enable non-secure access to these peripherals in order for the
  76          * OS to use these peripherals.
  77          */
  78         for (i = 0; i < ARRAY_SIZE(addr); i++)
  79                 writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
  80 }
  81
  82 void spl_disable_firewall_l4_sys(void)
  83 {
  84         const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
  85                 (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
  86         u32 i;
  87         const u32 *addr[] = {
  88                         &firwall_l4_sys_base->dma_ecc,
  89                         &firwall_l4_sys_base->emac0rx_ecc,
  90                         &firwall_l4_sys_base->emac0tx_ecc,
  91                         &firwall_l4_sys_base->emac1rx_ecc,
  92                         &firwall_l4_sys_base->emac1tx_ecc,
  93                         &firwall_l4_sys_base->emac2rx_ecc,
  94                         &firwall_l4_sys_base->emac2tx_ecc,
  95                         &firwall_l4_sys_base->nand_ecc,
  96                         &firwall_l4_sys_base->nand_read_ecc,
  97                         &firwall_l4_sys_base->nand_write_ecc,
  98                         &firwall_l4_sys_base->ocram_ecc,
  99                         &firwall_l4_sys_base->sdmmc_ecc,
 100                         &firwall_l4_sys_base->usb0_ecc,
 101                         &firwall_l4_sys_base->usb1_ecc,
 102                         &firwall_l4_sys_base->clock_manager,
 103                         &firwall_l4_sys_base->io_manager,
 104                         &firwall_l4_sys_base->reset_manager,
 105                         &firwall_l4_sys_base->system_manager,
 106                         &firwall_l4_sys_base->watchdog0,
 107                         &firwall_l4_sys_base->watchdog1,
 108                         &firwall_l4_sys_base->watchdog2,
 109                         &firwall_l4_sys_base->watchdog3
 110                 };
 111
 112         for (i = 0; i < ARRAY_SIZE(addr); i++)
 113                 writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
 114 }
 115
 116 void board_init_f(ulong dummy)
 117 {
 118         const struct cm_config *cm_default_cfg = cm_get_default_config();
 119         int ret;
 120
 121         ret = spl_early_init();
 122         if (ret)
 123                 hang();
 124
 125         socfpga_get_managers_addr();
 126
 127 #ifdef CONFIG_HW_WATCHDOG
 128         /* Ensure watchdog is paused when debugging is happening */
 129         writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
 130                socfpga_get_sysmgr_addr() + SYSMGR_S10_WDDBG);
 131
 132         /* Enable watchdog before initializing the HW */
 133         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 134         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 135         hw_watchdog_init();
 136 #endif
 137
 138         /* ensure all processors are not released prior Linux boot */
 139         writeq(0, CPU_RELEASE_ADDR);
 140
 141         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
 142         timer_init();
 143
 144         sysmgr_pinmux_init();
 145
 146         /* configuring the HPS clocks */
 147         cm_basic_init(cm_default_cfg);
 148
 149 #ifdef CONFIG_DEBUG_UART
 150         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 151         debug_uart_init();
 152 #endif
 153
 154         preloader_console_init();
 155         cm_print_clock_quick_summary();
 156
 157         /* enable non-secure interface to DMA330 DMA and peripherals */
 158         writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
 159                socfpga_get_sysmgr_addr() + SYSMGR_S10_DMA);
 160         writel(SYSMGR_DMAPERIPH_ALL_NS,
 161                socfpga_get_sysmgr_addr() + SYSMGR_S10_DMA_PERIPH);
 162
 163         spl_disable_firewall_l4_per();
 164
 165         spl_disable_firewall_l4_sys();
 166
 167         /* disable lwsocf2fpga and soc2fpga bridge security */
 168         writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
 169         writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
 170
 171         /* disable SMMU security */
 172         writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
 173
 174         /* disable ocram security at CCU for non secure access */
 175         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
 176                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
 177         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
 178                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
 179
 180 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
 181                 struct udevice *dev;
 182
 183                 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 184                 if (ret) {
 185                         debug("DRAM init failed: %d\n", ret);
 186                         hang();
 187                 }
 188 #endif
 189
 190         mbox_init();
 191
 192 #ifdef CONFIG_CADENCE_QSPI
 193         mbox_qspi_open();
 194 #endif
 195 }