arch/arm/mach-socfpga/spl_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <asm/pl310.h>
   9 #include <asm/u-boot.h>
  10 #include <asm/utils.h>
  11 #include <image.h>
  12 #include <asm/arch/reset_manager.h>
  13 #include <spl.h>
  14 #include <asm/arch/system_manager.h>
  15 #include <asm/arch/freeze_controller.h>
  16 #include <asm/arch/clock_manager.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20 #include <asm/arch/scu.h>
  21 #include <asm/arch/nic301.h>
  22 #include <asm/sections.h>
  23 #include <debug_uart.h>
  24 #include <fdtdec.h>
  25 #include <watchdog.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 static struct pl310_regs *const pl310 =
  30         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  31 static struct scu_registers *scu_regs =
  32         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  33 static struct nic301_registers *nic301_regs =
  34         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  35 static const struct socfpga_system_manager *sysmgr_regs =
  36         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  37
  38 u32 spl_boot_device(void)
  39 {
  40         const u32 bsel = readl(&sysmgr_regs->bootinfo);
  41
  42         switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  43         case 0x1:       /* FPGA (HPS2FPGA Bridge) */
  44                 return BOOT_DEVICE_RAM;
  45         case 0x2:       /* NAND Flash (1.8V) */
  46         case 0x3:       /* NAND Flash (3.0V) */
  47                 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  48                 return BOOT_DEVICE_NAND;
  49         case 0x4:       /* SD/MMC External Transceiver (1.8V) */
  50         case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
  51                 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  52                 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  53                 return BOOT_DEVICE_MMC1;
  54         case 0x6:       /* QSPI Flash (1.8V) */
  55         case 0x7:       /* QSPI Flash (3.0V) */
  56                 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  57                 return BOOT_DEVICE_SPI;
  58         default:
  59                 printf("Invalid boot device (bsel=%08x)!\n", bsel);
  60                 hang();
  61         }
  62 }
  63
  64 #ifdef CONFIG_SPL_MMC_SUPPORT
  65 u32 spl_boot_mode(const u32 boot_device)
  66 {
  67 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
  68         return MMCSD_MODE_FS;
  69 #else
  70         return MMCSD_MODE_RAW;
  71 #endif
  72 }
  73 #endif
  74
  75 static void socfpga_nic301_slave_ns(void)
  76 {
  77         writel(0x1, &nic301_regs->lwhps2fpgaregs);
  78         writel(0x1, &nic301_regs->hps2fpgaregs);
  79         writel(0x1, &nic301_regs->acp);
  80         writel(0x1, &nic301_regs->rom);
  81         writel(0x1, &nic301_regs->ocram);
  82         writel(0x1, &nic301_regs->sdrdata);
  83 }
  84
  85 void board_init_f(ulong dummy)
  86 {
  87         const struct cm_config *cm_default_cfg = cm_get_default_config();
  88         unsigned long sdram_size;
  89         unsigned long reg;
  90         int ret;
  91
  92         /*
  93          * First C code to run. Clear fake OCRAM ECC first as SBE
  94          * and DBE might triggered during power on
  95          */
  96         reg = readl(&sysmgr_regs->eccgrp_ocram);
  97         if (reg & SYSMGR_ECC_OCRAM_SERR)
  98                 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
  99                        &sysmgr_regs->eccgrp_ocram);
 100         if (reg & SYSMGR_ECC_OCRAM_DERR)
 101                 writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
 102                        &sysmgr_regs->eccgrp_ocram);
 103
 104         memset(__bss_start, 0, __bss_end - __bss_start);
 105
 106         socfpga_nic301_slave_ns();
 107
 108         /* Configure ARM MPU SNSAC register. */
 109         setbits_le32(&scu_regs->sacr, 0xfff);
 110
 111         /* Remap SDRAM to 0x0 */
 112         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 113         writel(0x1, &pl310->pl310_addr_filter_start);
 114
 115         debug("Freezing all I/O banks\n");
 116         /* freeze all IO banks */
 117         sys_mgr_frzctrl_freeze_req();
 118
 119         /* Put everything into reset but L4WD0. */
 120         socfpga_per_reset_all();
 121         /* Put FPGA bridges into reset too. */
 122         socfpga_bridges_reset(1);
 123
 124         socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
 125         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 126         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
 127
 128         timer_init();
 129
 130         debug("Reconfigure Clock Manager\n");
 131         /* reconfigure the PLLs */
 132         if (cm_basic_init(cm_default_cfg))
 133                 hang();
 134
 135         /* Enable bootrom to configure IOs. */
 136         sysmgr_config_warmrstcfgio(1);
 137
 138         /* configure the IOCSR / IO buffer settings */
 139         if (scan_mgr_configure_iocsr())
 140                 hang();
 141
 142         sysmgr_config_warmrstcfgio(0);
 143
 144         /* configure the pin muxing through system manager */
 145         sysmgr_config_warmrstcfgio(1);
 146         sysmgr_pinmux_init();
 147         sysmgr_config_warmrstcfgio(0);
 148
 149         /* De-assert reset for peripherals and bridges based on handoff */
 150         reset_deassert_peripherals_handoff();
 151         socfpga_bridges_reset(0);
 152
 153         debug("Unfreezing/Thaw all I/O banks\n");
 154         /* unfreeze / thaw all IO banks */
 155         sys_mgr_frzctrl_thaw_req();
 156
 157 #ifdef CONFIG_DEBUG_UART
 158         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 159         debug_uart_init();
 160 #endif
 161
 162         ret = spl_early_init();
 163         if (ret) {
 164                 debug("spl_early_init() failed: %d\n", ret);
 165                 hang();
 166         }
 167
 168         /* enable console uart printing */
 169         preloader_console_init();
 170
 171         if (sdram_mmr_init_full(0xffffffff) != 0) {
 172                 puts("SDRAM init failed.\n");
 173                 hang();
 174         }
 175
 176         debug("SDRAM: Calibrating PHY\n");
 177         /* SDRAM calibration */
 178         if (sdram_calibration_full() == 0) {
 179                 puts("SDRAM calibration failed.\n");
 180                 hang();
 181         }
 182
 183         sdram_size = sdram_calculate_size();
 184         debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 185
 186         /* Sanity check ensure correct SDRAM size specified */
 187         if (get_ram_size(0, sdram_size) != sdram_size) {
 188                 puts("SDRAM size check failed!\n");
 189                 hang();
 190         }
 191
 192         socfpga_bridges_reset(1);
 193 }