arch/arm/mach-socfpga/spl_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <asm/pl310.h>
   9 #include <asm/u-boot.h>
  10 #include <asm/utils.h>
  11 #include <image.h>
  12 #include <asm/arch/reset_manager.h>
  13 #include <spl.h>
  14 #include <asm/arch/system_manager.h>
  15 #include <asm/arch/freeze_controller.h>
  16 #include <asm/arch/clock_manager.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20 #include <asm/sections.h>
  21 #include <debug_uart.h>
  22 #include <fdtdec.h>
  23 #include <watchdog.h>
  24 #include <dm/uclass.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static struct pl310_regs *const pl310 =
  29         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  30 static const struct socfpga_system_manager *sysmgr_regs =
  31         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  32
  33 u32 spl_boot_device(void)
  34 {
  35         const u32 bsel = readl(&sysmgr_regs->bootinfo);
  36
  37         switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  38         case 0x1:       /* FPGA (HPS2FPGA Bridge) */
  39                 return BOOT_DEVICE_RAM;
  40         case 0x2:       /* NAND Flash (1.8V) */
  41         case 0x3:       /* NAND Flash (3.0V) */
  42                 return BOOT_DEVICE_NAND;
  43         case 0x4:       /* SD/MMC External Transceiver (1.8V) */
  44         case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
  45                 return BOOT_DEVICE_MMC1;
  46         case 0x6:       /* QSPI Flash (1.8V) */
  47         case 0x7:       /* QSPI Flash (3.0V) */
  48                 return BOOT_DEVICE_SPI;
  49         default:
  50                 printf("Invalid boot device (bsel=%08x)!\n", bsel);
  51                 hang();
  52         }
  53 }
  54
  55 #ifdef CONFIG_SPL_MMC_SUPPORT
  56 u32 spl_boot_mode(const u32 boot_device)
  57 {
  58 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  59         return MMCSD_MODE_FS;
  60 #else
  61         return MMCSD_MODE_RAW;
  62 #endif
  63 }
  64 #endif
  65
  66 static void socfpga_pl310_clear(void)
  67 {
  68         u32 mask = 0xff, ena = 0;
  69
  70         icache_enable();
  71
  72         /* Disable the L2 cache */
  73         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  74
  75         writel(0x111, &pl310->pl310_tag_latency_ctrl);
  76         writel(0x121, &pl310->pl310_data_latency_ctrl);
  77
  78         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  79         setbits_le32(&pl310->pl310_aux_ctrl,
  80                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  81                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  82                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  83
  84         /* Enable the L2 cache */
  85         ena = readl(&pl310->pl310_ctrl);
  86         ena |= L2X0_CTRL_EN;
  87
  88         /*
  89          * Invalidate the PL310 L2 cache. Keep the invalidation code
  90          * entirely in L1 I-cache to avoid any bus traffic through
  91          * the L2.
  92          */
  93         asm volatile(
  94                 ".align 5                       \n"
  95                 "       b       3f              \n"
  96                 "1:     str     %1,     [%4]    \n"
  97                 "       dsb                     \n"
  98                 "       isb                     \n"
  99                 "       str     %0,     [%2]    \n"
 100                 "       dsb                     \n"
 101                 "       isb                     \n"
 102                 "2:     ldr     %0,     [%2]    \n"
 103                 "       cmp     %0,     #0      \n"
 104                 "       bne     2b              \n"
 105                 "       str     %0,     [%3]    \n"
 106                 "       dsb                     \n"
 107                 "       isb                     \n"
 108                 "       b       4f              \n"
 109                 "3:     b       1b              \n"
 110                 "4:     nop                     \n"
 111         : "+r"(mask), "+r"(ena)
 112         : "r"(&pl310->pl310_inv_way),
 113           "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
 114         : "memory", "cc");
 115
 116         /* Disable the L2 cache */
 117         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 118 }
 119
 120 void board_init_f(ulong dummy)
 121 {
 122         const struct cm_config *cm_default_cfg = cm_get_default_config();
 123         unsigned long reg;
 124         int ret;
 125         struct udevice *dev;
 126
 127         /*
 128          * First C code to run. Clear fake OCRAM ECC first as SBE
 129          * and DBE might triggered during power on
 130          */
 131         reg = readl(&sysmgr_regs->eccgrp_ocram);
 132         if (reg & SYSMGR_ECC_OCRAM_SERR)
 133                 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
 134                        &sysmgr_regs->eccgrp_ocram);
 135         if (reg & SYSMGR_ECC_OCRAM_DERR)
 136                 writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
 137                        &sysmgr_regs->eccgrp_ocram);
 138
 139         memset(__bss_start, 0, __bss_end - __bss_start);
 140
 141         socfpga_sdram_remap_zero();
 142         socfpga_pl310_clear();
 143
 144         debug("Freezing all I/O banks\n");
 145         /* freeze all IO banks */
 146         sys_mgr_frzctrl_freeze_req();
 147
 148         /* Put everything into reset but L4WD0. */
 149         socfpga_per_reset_all();
 150
 151         if (!socfpga_is_booting_from_fpga()) {
 152                 /* Put FPGA bridges into reset too. */
 153                 socfpga_bridges_reset(1);
 154         }
 155
 156         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
 157         timer_init();
 158
 159         debug("Reconfigure Clock Manager\n");
 160         /* reconfigure the PLLs */
 161         if (cm_basic_init(cm_default_cfg))
 162                 hang();
 163
 164         /* Enable bootrom to configure IOs. */
 165         sysmgr_config_warmrstcfgio(1);
 166
 167         /* configure the IOCSR / IO buffer settings */
 168         if (scan_mgr_configure_iocsr())
 169                 hang();
 170
 171         sysmgr_config_warmrstcfgio(0);
 172
 173         /* configure the pin muxing through system manager */
 174         sysmgr_config_warmrstcfgio(1);
 175         sysmgr_pinmux_init();
 176         sysmgr_config_warmrstcfgio(0);
 177
 178         /* De-assert reset for peripherals and bridges based on handoff */
 179         reset_deassert_peripherals_handoff();
 180         socfpga_bridges_set_handoff_regs(true, true, true);
 181
 182         debug("Unfreezing/Thaw all I/O banks\n");
 183         /* unfreeze / thaw all IO banks */
 184         sys_mgr_frzctrl_thaw_req();
 185
 186 #ifdef CONFIG_DEBUG_UART
 187         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 188         debug_uart_init();
 189 #endif
 190
 191         ret = spl_early_init();
 192         if (ret) {
 193                 debug("spl_early_init() failed: %d\n", ret);
 194                 hang();
 195         }
 196
 197         ret = uclass_get_device(UCLASS_RESET, 0, &dev);
 198         if (ret)
 199                 debug("Reset init failed: %d\n", ret);
 200
 201         /* enable console uart printing */
 202         preloader_console_init();
 203
 204         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 205         if (ret) {
 206                 debug("DRAM init failed: %d\n", ret);
 207                 hang();
 208         }
 209 }