arch/arm/mach-socfpga/spl_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <asm/pl310.h>
   9 #include <asm/u-boot.h>
  10 #include <asm/utils.h>
  11 #include <image.h>
  12 #include <asm/arch/reset_manager.h>
  13 #include <spl.h>
  14 #include <asm/arch/system_manager.h>
  15 #include <asm/arch/freeze_controller.h>
  16 #include <asm/arch/clock_manager.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20 #include <asm/sections.h>
  21 #include <debug_uart.h>
  22 #include <fdtdec.h>
  23 #include <watchdog.h>
  24 #include <dm/uclass.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static struct pl310_regs *const pl310 =
  29         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  30 static const struct socfpga_system_manager *sysmgr_regs =
  31         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  32
  33 u32 spl_boot_device(void)
  34 {
  35         const u32 bsel = readl(&sysmgr_regs->bootinfo);
  36
  37         switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  38         case 0x1:       /* FPGA (HPS2FPGA Bridge) */
  39                 return BOOT_DEVICE_RAM;
  40         case 0x2:       /* NAND Flash (1.8V) */
  41         case 0x3:       /* NAND Flash (3.0V) */
  42                 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  43                 return BOOT_DEVICE_NAND;
  44         case 0x4:       /* SD/MMC External Transceiver (1.8V) */
  45         case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
  46                 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  47                 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  48                 return BOOT_DEVICE_MMC1;
  49         case 0x6:       /* QSPI Flash (1.8V) */
  50         case 0x7:       /* QSPI Flash (3.0V) */
  51                 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  52                 return BOOT_DEVICE_SPI;
  53         default:
  54                 printf("Invalid boot device (bsel=%08x)!\n", bsel);
  55                 hang();
  56         }
  57 }
  58
  59 #ifdef CONFIG_SPL_MMC_SUPPORT
  60 u32 spl_boot_mode(const u32 boot_device)
  61 {
  62 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  63         return MMCSD_MODE_FS;
  64 #else
  65         return MMCSD_MODE_RAW;
  66 #endif
  67 }
  68 #endif
  69
  70 static void socfpga_pl310_clear(void)
  71 {
  72         u32 mask = 0xff, ena = 0;
  73
  74         icache_enable();
  75
  76         /* Disable the L2 cache */
  77         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  78
  79         writel(0x111, &pl310->pl310_tag_latency_ctrl);
  80         writel(0x121, &pl310->pl310_data_latency_ctrl);
  81
  82         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  83         setbits_le32(&pl310->pl310_aux_ctrl,
  84                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  85                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  86                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  87
  88         /* Enable the L2 cache */
  89         ena = readl(&pl310->pl310_ctrl);
  90         ena |= L2X0_CTRL_EN;
  91
  92         /*
  93          * Invalidate the PL310 L2 cache. Keep the invalidation code
  94          * entirely in L1 I-cache to avoid any bus traffic through
  95          * the L2.
  96          */
  97         asm volatile(
  98                 ".align 5                       \n"
  99                 "       b       3f              \n"
 100                 "1:     str     %1,     [%4]    \n"
 101                 "       dsb                     \n"
 102                 "       isb                     \n"
 103                 "       str     %0,     [%2]    \n"
 104                 "       dsb                     \n"
 105                 "       isb                     \n"
 106                 "2:     ldr     %0,     [%2]    \n"
 107                 "       cmp     %0,     #0      \n"
 108                 "       bne     2b              \n"
 109                 "       str     %0,     [%3]    \n"
 110                 "       dsb                     \n"
 111                 "       isb                     \n"
 112                 "       b       4f              \n"
 113                 "3:     b       1b              \n"
 114                 "4:     nop                     \n"
 115         : "+r"(mask), "+r"(ena)
 116         : "r"(&pl310->pl310_inv_way),
 117           "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
 118         : "memory", "cc");
 119
 120         /* Disable the L2 cache */
 121         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 122 }
 123
 124 void board_init_f(ulong dummy)
 125 {
 126         const struct cm_config *cm_default_cfg = cm_get_default_config();
 127         unsigned long reg;
 128         int ret;
 129         struct udevice *dev;
 130
 131         /*
 132          * First C code to run. Clear fake OCRAM ECC first as SBE
 133          * and DBE might triggered during power on
 134          */
 135         reg = readl(&sysmgr_regs->eccgrp_ocram);
 136         if (reg & SYSMGR_ECC_OCRAM_SERR)
 137                 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
 138                        &sysmgr_regs->eccgrp_ocram);
 139         if (reg & SYSMGR_ECC_OCRAM_DERR)
 140                 writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
 141                        &sysmgr_regs->eccgrp_ocram);
 142
 143         memset(__bss_start, 0, __bss_end - __bss_start);
 144
 145         socfpga_sdram_remap_zero();
 146         socfpga_pl310_clear();
 147
 148         debug("Freezing all I/O banks\n");
 149         /* freeze all IO banks */
 150         sys_mgr_frzctrl_freeze_req();
 151
 152         /* Put everything into reset but L4WD0. */
 153         socfpga_per_reset_all();
 154
 155         if (!socfpga_is_booting_from_fpga()) {
 156                 /* Put FPGA bridges into reset too. */
 157                 socfpga_bridges_reset(1);
 158         }
 159
 160         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 161         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
 162
 163         timer_init();
 164
 165         debug("Reconfigure Clock Manager\n");
 166         /* reconfigure the PLLs */
 167         if (cm_basic_init(cm_default_cfg))
 168                 hang();
 169
 170         /* Enable bootrom to configure IOs. */
 171         sysmgr_config_warmrstcfgio(1);
 172
 173         /* configure the IOCSR / IO buffer settings */
 174         if (scan_mgr_configure_iocsr())
 175                 hang();
 176
 177         sysmgr_config_warmrstcfgio(0);
 178
 179         /* configure the pin muxing through system manager */
 180         sysmgr_config_warmrstcfgio(1);
 181         sysmgr_pinmux_init();
 182         sysmgr_config_warmrstcfgio(0);
 183
 184         /* De-assert reset for peripherals and bridges based on handoff */
 185         reset_deassert_peripherals_handoff();
 186         socfpga_bridges_reset(0);
 187
 188         debug("Unfreezing/Thaw all I/O banks\n");
 189         /* unfreeze / thaw all IO banks */
 190         sys_mgr_frzctrl_thaw_req();
 191
 192 #ifdef CONFIG_DEBUG_UART
 193         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 194         debug_uart_init();
 195 #endif
 196
 197         ret = spl_early_init();
 198         if (ret) {
 199                 debug("spl_early_init() failed: %d\n", ret);
 200                 hang();
 201         }
 202
 203         ret = uclass_get_device(UCLASS_RESET, 0, &dev);
 204         if (ret)
 205                 debug("Reset init failed: %d\n", ret);
 206
 207         /* enable console uart printing */
 208         preloader_console_init();
 209
 210         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 211         if (ret) {
 212                 debug("DRAM init failed: %d\n", ret);
 213                 hang();
 214         }
 215
 216         if (!socfpga_is_booting_from_fpga())
 217                 socfpga_bridges_reset(1);
 218 }