1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
8 #include <asm/u-boot.h>
11 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h>
14 #include <asm/arch/freeze_controller.h>
15 #include <asm/arch/clock_manager.h>
16 #include <asm/arch/misc.h>
17 #include <asm/arch/scan_manager.h>
18 #include <asm/arch/sdram.h>
19 #include <asm/sections.h>
20 #include <debug_uart.h>
23 #include <dm/uclass.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 u32 spl_boot_device(void)
29 const u32 bsel = readl(socfpga_get_sysmgr_addr() +
30 SYSMGR_GEN5_BOOTINFO);
32 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
33 case 0x1: /* FPGA (HPS2FPGA Bridge) */
34 return BOOT_DEVICE_RAM;
35 case 0x2: /* NAND Flash (1.8V) */
36 case 0x3: /* NAND Flash (3.0V) */
37 return BOOT_DEVICE_NAND;
38 case 0x4: /* SD/MMC External Transceiver (1.8V) */
39 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
40 return BOOT_DEVICE_MMC1;
41 case 0x6: /* QSPI Flash (1.8V) */
42 case 0x7: /* QSPI Flash (3.0V) */
43 return BOOT_DEVICE_SPI;
45 printf("Invalid boot device (bsel=%08x)!\n", bsel);
50 #ifdef CONFIG_SPL_MMC_SUPPORT
51 u32 spl_boot_mode(const u32 boot_device)
53 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
56 return MMCSD_MODE_RAW;
61 void board_init_f(ulong dummy)
63 const struct cm_config *cm_default_cfg = cm_get_default_config();
68 ret = spl_early_init();
72 socfpga_get_managers_addr();
75 * Clear fake OCRAM ECC first as SBE
76 * and DBE might triggered during power on
78 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
79 if (reg & SYSMGR_ECC_OCRAM_SERR)
80 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
81 socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
82 if (reg & SYSMGR_ECC_OCRAM_DERR)
83 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
84 socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
86 socfpga_sdram_remap_zero();
87 socfpga_pl310_clear();
89 debug("Freezing all I/O banks\n");
90 /* freeze all IO banks */
91 sys_mgr_frzctrl_freeze_req();
93 /* Put everything into reset but L4WD0. */
94 socfpga_per_reset_all();
96 if (!socfpga_is_booting_from_fpga()) {
97 /* Put FPGA bridges into reset too. */
98 socfpga_bridges_reset(1);
101 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
104 debug("Reconfigure Clock Manager\n");
105 /* reconfigure the PLLs */
106 if (cm_basic_init(cm_default_cfg))
109 /* Enable bootrom to configure IOs. */
110 sysmgr_config_warmrstcfgio(1);
112 /* configure the IOCSR / IO buffer settings */
113 if (scan_mgr_configure_iocsr())
116 sysmgr_config_warmrstcfgio(0);
118 /* configure the pin muxing through system manager */
119 sysmgr_config_warmrstcfgio(1);
120 sysmgr_pinmux_init();
121 sysmgr_config_warmrstcfgio(0);
123 /* Set bridges handoff value */
124 socfpga_bridges_set_handoff_regs(true, true, true);
126 debug("Unfreezing/Thaw all I/O banks\n");
127 /* unfreeze / thaw all IO banks */
128 sys_mgr_frzctrl_thaw_req();
130 #ifdef CONFIG_DEBUG_UART
131 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
135 ret = uclass_get_device(UCLASS_RESET, 0, &dev);
137 debug("Reset init failed: %d\n", ret);
139 #ifdef CONFIG_SPL_NAND_DENALI
140 struct socfpga_reset_manager *reset_manager_base =
141 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
143 clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4));
146 /* enable console uart printing */
147 preloader_console_init();
149 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
151 debug("DRAM init failed: %d\n", ret);