arch/arm/mach-socfpga/spl_a10.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <asm/pl310.h>
   9 #include <asm/u-boot.h>
  10 #include <asm/utils.h>
  11 #include <image.h>
  12 #include <asm/arch/reset_manager.h>
  13 #include <spl.h>
  14 #include <asm/arch/system_manager.h>
  15 #include <asm/arch/freeze_controller.h>
  16 #include <asm/arch/clock_manager.h>
  17 #include <asm/arch/scan_manager.h>
  18 #include <asm/arch/sdram.h>
  19 #include <asm/arch/scu.h>
  20 #include <asm/arch/misc.h>
  21 #include <asm/arch/nic301.h>
  22 #include <asm/sections.h>
  23 #include <fdtdec.h>
  24 #include <watchdog.h>
  25 #include <asm/arch/pinmux.h>
  26 #include <asm/arch/fpga_manager.h>
  27 #include <mmc.h>
  28 #include <memalign.h>
  29
  30 #define FPGA_BUFSIZ     16 * 1024
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 static const struct socfpga_system_manager *sysmgr_regs =
  35         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  36
  37 u32 spl_boot_device(void)
  38 {
  39         const u32 bsel = readl(&sysmgr_regs->bootinfo);
  40
  41         switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  42         case 0x1:       /* FPGA (HPS2FPGA Bridge) */
  43                 return BOOT_DEVICE_RAM;
  44         case 0x2:       /* NAND Flash (1.8V) */
  45         case 0x3:       /* NAND Flash (3.0V) */
  46                 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  47                 return BOOT_DEVICE_NAND;
  48         case 0x4:       /* SD/MMC External Transceiver (1.8V) */
  49         case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
  50                 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  51                 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  52                 return BOOT_DEVICE_MMC1;
  53         case 0x6:       /* QSPI Flash (1.8V) */
  54         case 0x7:       /* QSPI Flash (3.0V) */
  55                 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  56                 return BOOT_DEVICE_SPI;
  57         default:
  58                 printf("Invalid boot device (bsel=%08x)!\n", bsel);
  59                 hang();
  60         }
  61 }
  62
  63 #ifdef CONFIG_SPL_MMC_SUPPORT
  64 u32 spl_boot_mode(const u32 boot_device)
  65 {
  66 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  67         return MMCSD_MODE_FS;
  68 #else
  69         return MMCSD_MODE_RAW;
  70 #endif
  71 }
  72 #endif
  73
  74 void spl_board_init(void)
  75 {
  76         ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
  77
  78         /* enable console uart printing */
  79         preloader_console_init();
  80         WATCHDOG_RESET();
  81
  82         arch_early_init_r();
  83
  84         /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
  85         if (is_fpgamgr_user_mode()) {
  86                 int ret = config_pins(gd->fdt_blob, "shared");
  87
  88                 if (ret)
  89                         return;
  90
  91                 ret = config_pins(gd->fdt_blob, "fpga");
  92                 if (ret)
  93                         return;
  94         } else if (!is_fpgamgr_early_user_mode()) {
  95                 /* Program IOSSM(early IO release) or full FPGA */
  96                 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  97         }
  98
  99         /* If the IOSSM/full FPGA is already loaded, start DDR */
 100         if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
 101                 ddr_calibration_sequence();
 102
 103         if (!is_fpgamgr_user_mode())
 104                 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
 105 }
 106
 107 void board_init_f(ulong dummy)
 108 {
 109         dcache_disable();
 110
 111         socfpga_init_security_policies();
 112         socfpga_sdram_remap_zero();
 113         socfpga_pl310_clear();
 114
 115         /* Assert reset to all except L4WD0 and L4TIMER0 */
 116         socfpga_per_reset_all();
 117         socfpga_watchdog_disable();
 118
 119         spl_early_init();
 120
 121         /* Configure the clock based on handoff */
 122         cm_basic_init(gd->fdt_blob);
 123
 124 #ifdef CONFIG_HW_WATCHDOG
 125         /* release osc1 watchdog timer 0 from reset */
 126         socfpga_reset_deassert_osc1wd0();
 127
 128         /* reconfigure and enable the watchdog */
 129         hw_watchdog_init();
 130         WATCHDOG_RESET();
 131 #endif /* CONFIG_HW_WATCHDOG */
 132
 133         config_dedicated_pins(gd->fdt_blob);
 134         WATCHDOG_RESET();
 135 }