arch/arm/mach-socfpga/spl_a10.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <asm/io.h>
   9 #include <asm/pl310.h>
  10 #include <asm/u-boot.h>
  11 #include <asm/utils.h>
  12 #include <image.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <spl.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/freeze_controller.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20 #include <asm/arch/scu.h>
  21 #include <asm/arch/misc.h>
  22 #include <asm/arch/nic301.h>
  23 #include <asm/sections.h>
  24 #include <fdtdec.h>
  25 #include <watchdog.h>
  26 #include <asm/arch/pinmux.h>
  27 #include <asm/arch/fpga_manager.h>
  28 #include <mmc.h>
  29 #include <memalign.h>
  30
  31 #define FPGA_BUFSIZ     16 * 1024
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 u32 spl_boot_device(void)
  36 {
  37         const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
  38
  39         switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  40         case 0x1:       /* FPGA (HPS2FPGA Bridge) */
  41                 return BOOT_DEVICE_RAM;
  42         case 0x2:       /* NAND Flash (1.8V) */
  43         case 0x3:       /* NAND Flash (3.0V) */
  44                 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  45                 return BOOT_DEVICE_NAND;
  46         case 0x4:       /* SD/MMC External Transceiver (1.8V) */
  47         case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
  48                 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  49                 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  50                 return BOOT_DEVICE_MMC1;
  51         case 0x6:       /* QSPI Flash (1.8V) */
  52         case 0x7:       /* QSPI Flash (3.0V) */
  53                 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  54                 return BOOT_DEVICE_SPI;
  55         default:
  56                 printf("Invalid boot device (bsel=%08x)!\n", bsel);
  57                 hang();
  58         }
  59 }
  60
  61 #ifdef CONFIG_SPL_MMC_SUPPORT
  62 u32 spl_boot_mode(const u32 boot_device)
  63 {
  64 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  65         return MMCSD_MODE_FS;
  66 #else
  67         return MMCSD_MODE_RAW;
  68 #endif
  69 }
  70 #endif
  71
  72 void spl_board_init(void)
  73 {
  74         ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
  75
  76         /* enable console uart printing */
  77         preloader_console_init();
  78         WATCHDOG_RESET();
  79
  80         arch_early_init_r();
  81
  82         /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
  83         if (is_fpgamgr_user_mode()) {
  84                 int ret = config_pins(gd->fdt_blob, "shared");
  85
  86                 if (ret)
  87                         return;
  88
  89                 ret = config_pins(gd->fdt_blob, "fpga");
  90                 if (ret)
  91                         return;
  92         } else if (!is_fpgamgr_early_user_mode()) {
  93                 /* Program IOSSM(early IO release) or full FPGA */
  94                 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  95         }
  96
  97         /* If the IOSSM/full FPGA is already loaded, start DDR */
  98         if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
  99                 ddr_calibration_sequence();
 100
 101         if (!is_fpgamgr_user_mode())
 102                 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
 103 }
 104
 105 void board_init_f(ulong dummy)
 106 {
 107         if (spl_early_init())
 108                 hang();
 109
 110         socfpga_get_managers_addr();
 111
 112         dcache_disable();
 113
 114         socfpga_init_security_policies();
 115         socfpga_sdram_remap_zero();
 116         socfpga_pl310_clear();
 117
 118         /* Assert reset to all except L4WD0 and L4TIMER0 */
 119         socfpga_per_reset_all();
 120         socfpga_watchdog_disable();
 121
 122         /* Configure the clock based on handoff */
 123         cm_basic_init(gd->fdt_blob);
 124
 125 #ifdef CONFIG_HW_WATCHDOG
 126         /* release osc1 watchdog timer 0 from reset */
 127         socfpga_reset_deassert_osc1wd0();
 128
 129         /* reconfigure and enable the watchdog */
 130         hw_watchdog_init();
 131         WATCHDOG_RESET();
 132 #endif /* CONFIG_HW_WATCHDOG */
 133
 134         config_dedicated_pins(gd->fdt_blob);
 135         WATCHDOG_RESET();
 136 }