arch/arm/mach-socfpga/spl_a10.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <hang.h>
   9 #include <asm/io.h>
  10 #include <asm/pl310.h>
  11 #include <asm/u-boot.h>
  12 #include <asm/utils.h>
  13 #include <image.h>
  14 #include <asm/arch/reset_manager.h>
  15 #include <spl.h>
  16 #include <asm/arch/system_manager.h>
  17 #include <asm/arch/freeze_controller.h>
  18 #include <asm/arch/clock_manager.h>
  19 #include <asm/arch/scan_manager.h>
  20 #include <asm/arch/sdram.h>
  21 #include <asm/arch/scu.h>
  22 #include <asm/arch/misc.h>
  23 #include <asm/arch/nic301.h>
  24 #include <asm/sections.h>
  25 #include <fdtdec.h>
  26 #include <watchdog.h>
  27 #include <asm/arch/pinmux.h>
  28 #include <asm/arch/fpga_manager.h>
  29 #include <mmc.h>
  30 #include <memalign.h>
  31
  32 #define FPGA_BUFSIZ     16 * 1024
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 u32 spl_boot_device(void)
  37 {
  38         const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
  39
  40         switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  41         case 0x1:       /* FPGA (HPS2FPGA Bridge) */
  42                 return BOOT_DEVICE_RAM;
  43         case 0x2:       /* NAND Flash (1.8V) */
  44         case 0x3:       /* NAND Flash (3.0V) */
  45                 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  46                 return BOOT_DEVICE_NAND;
  47         case 0x4:       /* SD/MMC External Transceiver (1.8V) */
  48         case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
  49                 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  50                 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  51                 return BOOT_DEVICE_MMC1;
  52         case 0x6:       /* QSPI Flash (1.8V) */
  53         case 0x7:       /* QSPI Flash (3.0V) */
  54                 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  55                 return BOOT_DEVICE_SPI;
  56         default:
  57                 printf("Invalid boot device (bsel=%08x)!\n", bsel);
  58                 hang();
  59         }
  60 }
  61
  62 #ifdef CONFIG_SPL_MMC_SUPPORT
  63 u32 spl_boot_mode(const u32 boot_device)
  64 {
  65 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  66         return MMCSD_MODE_FS;
  67 #else
  68         return MMCSD_MODE_RAW;
  69 #endif
  70 }
  71 #endif
  72
  73 void spl_board_init(void)
  74 {
  75         ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
  76
  77         /* enable console uart printing */
  78         preloader_console_init();
  79         WATCHDOG_RESET();
  80
  81         arch_early_init_r();
  82
  83         /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
  84         if (is_fpgamgr_user_mode()) {
  85                 int ret = config_pins(gd->fdt_blob, "shared");
  86
  87                 if (ret)
  88                         return;
  89
  90                 ret = config_pins(gd->fdt_blob, "fpga");
  91                 if (ret)
  92                         return;
  93         } else if (!is_fpgamgr_early_user_mode()) {
  94                 /* Program IOSSM(early IO release) or full FPGA */
  95                 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  96         }
  97
  98         /* If the IOSSM/full FPGA is already loaded, start DDR */
  99         if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
 100                 ddr_calibration_sequence();
 101
 102         if (!is_fpgamgr_user_mode())
 103                 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
 104 }
 105
 106 void board_init_f(ulong dummy)
 107 {
 108         if (spl_early_init())
 109                 hang();
 110
 111         socfpga_get_managers_addr();
 112
 113         dcache_disable();
 114
 115         socfpga_init_security_policies();
 116         socfpga_sdram_remap_zero();
 117         socfpga_pl310_clear();
 118
 119         /* Assert reset to all except L4WD0 and L4TIMER0 */
 120         socfpga_per_reset_all();
 121         socfpga_watchdog_disable();
 122
 123         /* Configure the clock based on handoff */
 124         cm_basic_init(gd->fdt_blob);
 125
 126 #ifdef CONFIG_HW_WATCHDOG
 127         /* release osc1 watchdog timer 0 from reset */
 128         socfpga_reset_deassert_osc1wd0();
 129
 130         /* reconfigure and enable the watchdog */
 131         hw_watchdog_init();
 132         WATCHDOG_RESET();
 133 #endif /* CONFIG_HW_WATCHDOG */
 134
 135         config_dedicated_pins(gd->fdt_blob);
 136         WATCHDOG_RESET();
 137 }