arch/arm/mach-socfpga/misc_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <altera.h>
   8 #include <common.h>
   9 #include <env.h>
  10 #include <errno.h>
  11 #include <fdtdec.h>
  12 #include <miiphy.h>
  13 #include <netdev.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/reset_manager.h>
  16 #include <asm/arch/system_manager.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/pl310.h>
  19 #include <linux/libfdt.h>
  20 #include <asm/arch/mailbox_s10.h>
  21
  22 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 static struct socfpga_system_manager *sysmgr_regs =
  27         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  28
  29 /*
  30  * FPGA programming support for SoC FPGA Stratix 10
  31  */
  32 static Altera_desc altera_fpga[] = {
  33         {
  34                 /* Family */
  35                 Intel_FPGA_Stratix10,
  36                 /* Interface type */
  37                 secure_device_manager_mailbox,
  38                 /* No limitation as additional data will be ignored */
  39                 -1,
  40                 /* No device function table */
  41                 NULL,
  42                 /* Base interface address specified in driver */
  43                 NULL,
  44                 /* No cookie implementation */
  45                 0
  46         },
  47 };
  48
  49 /*
  50  * DesignWare Ethernet initialization
  51  */
  52 #ifdef CONFIG_ETH_DESIGNWARE
  53
  54 static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
  55 {
  56         u32 modereg;
  57
  58         if (!phymode)
  59                 return -EINVAL;
  60
  61         if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
  62             !strcmp(phymode, "sgmii"))
  63                 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
  64         else if (!strcmp(phymode, "rgmii"))
  65                 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
  66         else if (!strcmp(phymode, "rmii"))
  67                 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
  68         else
  69                 return -EINVAL;
  70
  71         clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
  72                         SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
  73                         modereg);
  74
  75         return 0;
  76 }
  77
  78 static int socfpga_set_phymode(void)
  79 {
  80         const void *fdt = gd->fdt_blob;
  81         struct fdtdec_phandle_args args;
  82         const char *phy_mode;
  83         u32 gmac_index;
  84         int nodes[3];   /* Max. 3 GMACs */
  85         int ret, count;
  86         int i, node;
  87
  88         count = fdtdec_find_aliases_for_id(fdt, "ethernet",
  89                                            COMPAT_ALTERA_SOCFPGA_DWMAC,
  90                                            nodes, ARRAY_SIZE(nodes));
  91         for (i = 0; i < count; i++) {
  92                 node = nodes[i];
  93                 if (node <= 0)
  94                         continue;
  95
  96                 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
  97                                                      "#reset-cells", 1, 0,
  98                                                      &args);
  99                 if (ret || args.args_count != 1) {
 100                         debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
 101                         continue;
 102                 }
 103
 104                 gmac_index = args.args[0] - EMAC0_RESET;
 105
 106                 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
 107                 ret = socfpga_phymode_setup(gmac_index, phy_mode);
 108                 if (ret) {
 109                         debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
 110                         continue;
 111                 }
 112         }
 113
 114         return 0;
 115 }
 116 #else
 117 static int socfpga_set_phymode(void)
 118 {
 119         return 0;
 120 };
 121 #endif
 122
 123 /*
 124  * Print CPU information
 125  */
 126 #if defined(CONFIG_DISPLAY_CPUINFO)
 127 int print_cpuinfo(void)
 128 {
 129         puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
 130
 131         return 0;
 132 }
 133 #endif
 134
 135 #ifdef CONFIG_ARCH_MISC_INIT
 136 int arch_misc_init(void)
 137 {
 138         char qspi_string[13];
 139
 140         sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
 141         env_set("qspi_clock", qspi_string);
 142
 143         socfpga_set_phymode();
 144         return 0;
 145 }
 146 #endif
 147
 148 int arch_early_init_r(void)
 149 {
 150         socfpga_fpga_add(&altera_fpga[0]);
 151
 152         return 0;
 153 }
 154
 155 void do_bridge_reset(int enable, unsigned int mask)
 156 {
 157         /* Check FPGA status before bridge enable */
 158         if (enable) {
 159                 int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
 160
 161                 if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
 162                         ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
 163
 164                 if (ret)
 165                         return;
 166         }
 167
 168         socfpga_bridges_reset(enable);
 169 }